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add pattern to load constant 0 into a predicate reg

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24164 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Duraid Madina 2005-11-03 10:09:32 +00:00
parent 2b11995547
commit 0e5e0d14a8
1 changed files with 2 additions and 0 deletions
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lib/Target/IA64/IA64InstrInfo.td
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@ -361,6 +361,8 @@ def SELECTINT : Pat<(select PR:$which, GR:$src1, GR:$src2),
def : Pat<(i64 immSExt14:$imm), (ADDS r0, immSExt14:$imm)>;
def : Pat<(i64 imm64:$imm), (MOVL imm64:$imm)>;
def : Pat<(i1 -1), (CMPEQ r0, r0)>; // TODO: this should just be a ref to p0
def : Pat<(i1 0), (CMPNE r0, r0)>; // TODO: any instruction actually *using*
// this predicate should be killed!
// TODO: support postincrement (reg, imm9) loads+stores - this needs more
// tablegen support