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Add an intrinsic for the SSE2 PAUSE instruction.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195697 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Cameron McInally 2013-11-26 00:20:43 +00:00
parent 0487c74613
commit 0e6ec124d5
3 changed files with 12 additions and 1 deletions
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2
include/llvm/IR/IntrinsicsX86.td
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@ -536,6 +536,8 @@ let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
Intrinsic<[], [], []>;
def int_x86_sse2_mfence : GCCBuiltin<"__builtin_ia32_mfence">,
Intrinsic<[], [], []>;
def int_x86_sse2_pause : GCCBuiltin<"__builtin_ia32_pause">,
Intrinsic<[], [], []>;
}
//===----------------------------------------------------------------------===//

4
lib/Target/X86/X86InstrSSE.td
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@ -3499,7 +3499,9 @@ def CLFLUSH : I<0xAE, MRM7m, (outs), (ins i8mem:$src),
// Pause. This "instruction" is encoded as "rep; nop", so even though it
// was introduced with SSE2, it's backward compatible.
def PAUSE : I<0x90, RawFrm, (outs), (ins), "pause", [], IIC_SSE_PAUSE>, REP;
def PAUSE : I<0x90, RawFrm, (outs), (ins),
"pause", [(int_x86_sse2_pause)], IIC_SSE_PAUSE>,
REP, Requires<[HasSSE2]>;
// Load, store, and memory fence
def SFENCE : I<0xAE, MRM_F8, (outs), (ins),

7
test/CodeGen/X86/sse2-intrinsics-x86.ll
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@ -710,3 +710,10 @@ define i32 @test_x86_sse2_ucomineq_sd(<2 x double> %a0, <2 x double> %a1) {
ret i32 %res
}
declare i32 @llvm.x86.sse2.ucomineq.sd(<2 x double>, <2 x double>) nounwind readnone
define void @test_x86_sse2_pause() {
; CHECK: pause
tail call void @llvm.x86.sse2.pause()
ret void
}
declare void @llvm.x86.sse2.pause() nounwind