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Add PPC64 mulli pattern
The PPC backend had been missing a pattern to generate mulli for 64-bit multiples. We had been generating it only for 32-bit multiplies. Unfortunately, generating li + mulld unnecessarily increases register pressure. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187807 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -542,6 +542,9 @@ defm DIVDU : XOForm_1r<31, 457, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
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defm MULLD : XOForm_1r<31, 233, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
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"mulld", "$rT, $rA, $rB", IntMulHD,
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[(set i64:$rT, (mul i64:$rA, i64:$rB))]>, isPPC64;
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def MULLI8 : DForm_2<7, (outs g8rc:$rD), (ins g8rc:$rA, s16imm64:$imm),
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"mulli $rD, $rA, $imm", IntMulLI,
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[(set i64:$rD, (mul i64:$rA, imm64SExt16:$imm))]>;
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}
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let neverHasSideEffects = 1 in {
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16
test/CodeGen/PowerPC/mulli64.ll
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16
test/CodeGen/PowerPC/mulli64.ll
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@ -0,0 +1,16 @@
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; RUN: llc -mcpu=pwr7 -mtriple=powerpc64-unknown-linux-gnu < %s | FileCheck %s
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target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
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target triple = "powerpc64-unknown-linux-gnu"
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define i64 @foo(i64 %a) #0 {
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entry:
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%mul = mul nsw i64 %a, 3
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ret i64 %mul
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}
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; CHECK-LABEL: @foo
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; CHECK: mulli 3, 3, 3
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; CHECK: blr
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attributes #0 = { nounwind readnone }
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