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https://github.com/c64scene-ar/llvm-6502.git
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ARM64: use regalloc-friendly COPY_TO_REGCLASS for bitcasts
The previous patterns directly inserted FMOV or INS instructions into the DAG for scalar_to_vector & bitconvert patterns. This is horribly inefficient and can generated lots more GPR <-> FPR register traffic than necessary. It's much better to emit instructions the register allocator understands so it can coalesce the copies when appropriate. It led to at least one ISelLowering hack to avoid the problems, which was incorrect for v1i64 (FPR64 has no dsub). It can now be removed entirely. This should also fix PR19331. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205616 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Tim Northover
parent
604dff27c9
commit
0eb313be18
@ -480,7 +480,6 @@ void ARM64TargetLowering::addTypeForNEON(EVT VT, EVT PromotedBitwiseVT) {
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setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT.getSimpleVT(), Custom);
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setOperationAction(ISD::INSERT_VECTOR_ELT, VT.getSimpleVT(), Custom);
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setOperationAction(ISD::SCALAR_TO_VECTOR, VT.getSimpleVT(), Custom);
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setOperationAction(ISD::BUILD_VECTOR, VT.getSimpleVT(), Custom);
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setOperationAction(ISD::VECTOR_SHUFFLE, VT.getSimpleVT(), Custom);
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setOperationAction(ISD::EXTRACT_SUBVECTOR, VT.getSimpleVT(), Custom);
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@ -1973,8 +1972,6 @@ SDValue ARM64TargetLowering::LowerOperation(SDValue Op,
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return LowerINSERT_VECTOR_ELT(Op, DAG);
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case ISD::EXTRACT_VECTOR_ELT:
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return LowerEXTRACT_VECTOR_ELT(Op, DAG);
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case ISD::SCALAR_TO_VECTOR:
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return LowerSCALAR_TO_VECTOR(Op, DAG);
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case ISD::BUILD_VECTOR:
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return LowerBUILD_VECTOR(Op, DAG);
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case ISD::VECTOR_SHUFFLE:
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@ -5577,53 +5574,6 @@ SDValue ARM64TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
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Op.getOperand(1));
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}
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SDValue ARM64TargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op,
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SelectionDAG &DAG) const {
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assert(Op.getOpcode() == ISD::SCALAR_TO_VECTOR && "Unknown opcode!");
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// Some AdvSIMD intrinsics leave their results in the scalar B/H/S/D
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// registers. The default lowering will copy those to a GPR then back
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// to a vector register. Instead, just recognize those cases and reference
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// the vector register they're already a subreg of.
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SDValue Op0 = Op->getOperand(0);
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if (Op0->getOpcode() != ISD::INTRINSIC_WO_CHAIN)
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return Op;
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unsigned IID = getIntrinsicID(Op0.getNode());
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// The below list of intrinsics isn't exhaustive. Add cases as-needed.
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// FIXME: Even better would be if there were an attribute on the node
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// that we could query and set in the intrinsics definition or something.
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unsigned SubIdx;
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switch (IID) {
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default:
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// Early exit if this isn't one of the intrinsics we handle.
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return Op;
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case Intrinsic::arm64_neon_uaddv:
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case Intrinsic::arm64_neon_saddv:
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case Intrinsic::arm64_neon_uaddlv:
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case Intrinsic::arm64_neon_saddlv:
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switch (Op0.getValueType().getSizeInBits()) {
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default:
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llvm_unreachable("Illegal result size from ARM64 vector intrinsic!");
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case 8:
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SubIdx = ARM64::bsub;
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break;
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case 16:
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SubIdx = ARM64::hsub;
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break;
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case 32:
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SubIdx = ARM64::ssub;
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break;
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case 64:
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SubIdx = ARM64::dsub;
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break;
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}
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}
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MachineSDNode *N =
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DAG.getMachineNode(TargetOpcode::INSERT_SUBREG, SDLoc(Op),
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Op.getValueType(), DAG.getUNDEF(Op.getValueType()),
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Op0, DAG.getTargetConstant(SubIdx, MVT::i32));
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return SDValue(N, 0);
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}
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SDValue ARM64TargetLowering::LowerEXTRACT_SUBVECTOR(SDValue Op,
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SelectionDAG &DAG) const {
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EVT VT = Op.getOperand(0).getValueType();
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@ -1890,31 +1890,39 @@ defm FMOV : UnscaledConversion<"fmov">;
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def : Pat<(f32 (fpimm0)), (FMOVWSr WZR)>, Requires<[NoZCZ]>;
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def : Pat<(f64 (fpimm0)), (FMOVXDr XZR)>, Requires<[NoZCZ]>;
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def : Pat<(v8i8 (bitconvert GPR64:$Xn)), (FMOVXDr GPR64:$Xn)>;
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def : Pat<(v4i16 (bitconvert GPR64:$Xn)), (FMOVXDr GPR64:$Xn)>;
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def : Pat<(v2i32 (bitconvert GPR64:$Xn)), (FMOVXDr GPR64:$Xn)>;
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def : Pat<(v1i64 (bitconvert GPR64:$Xn)), (FMOVXDr GPR64:$Xn)>;
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def : Pat<(v2f32 (bitconvert GPR64:$Xn)), (FMOVXDr GPR64:$Xn)>;
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def : Pat<(v1f64 (bitconvert GPR64:$Xn)), (FMOVXDr GPR64:$Xn)>;
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def : Pat<(v1i64 (scalar_to_vector GPR64:$Xn)), (FMOVXDr GPR64:$Xn)>;
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def : Pat<(v1f64 (scalar_to_vector GPR64:$Xn)), (FMOVXDr GPR64:$Xn)>;
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def : Pat<(v8i8 (bitconvert GPR64:$Xn)), (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
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def : Pat<(v4i16 (bitconvert GPR64:$Xn)), (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
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def : Pat<(v2i32 (bitconvert GPR64:$Xn)), (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
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def : Pat<(v1i64 (bitconvert GPR64:$Xn)), (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
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def : Pat<(v2f32 (bitconvert GPR64:$Xn)), (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
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def : Pat<(v1f64 (bitconvert GPR64:$Xn)), (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
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def : Pat<(v1i64 (scalar_to_vector GPR64:$Xn)),
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(COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
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def : Pat<(v1f64 (scalar_to_vector GPR64:$Xn)),
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(COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
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def : Pat<(v1f64 (scalar_to_vector (f64 FPR64:$Xn))), (v1f64 FPR64:$Xn)>;
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def : Pat<(i64 (bitconvert (v8i8 V64:$Vn))), (FMOVDXr V64:$Vn)>;
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def : Pat<(i64 (bitconvert (v4i16 V64:$Vn))), (FMOVDXr V64:$Vn)>;
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def : Pat<(i64 (bitconvert (v2i32 V64:$Vn))), (FMOVDXr V64:$Vn)>;
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def : Pat<(i64 (bitconvert (v1i64 V64:$Vn))), (FMOVDXr V64:$Vn)>;
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def : Pat<(i64 (bitconvert (v2f32 V64:$Vn))), (FMOVDXr V64:$Vn)>;
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def : Pat<(i64 (bitconvert (v1f64 V64:$Vn))), (FMOVDXr V64:$Vn)>;
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def : Pat<(i64 (bitconvert (v8i8 V64:$Vn))),
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(COPY_TO_REGCLASS V64:$Vn, GPR64)>;
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def : Pat<(i64 (bitconvert (v4i16 V64:$Vn))),
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(COPY_TO_REGCLASS V64:$Vn, GPR64)>;
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def : Pat<(i64 (bitconvert (v2i32 V64:$Vn))),
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(COPY_TO_REGCLASS V64:$Vn, GPR64)>;
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def : Pat<(i64 (bitconvert (v1i64 V64:$Vn))),
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(COPY_TO_REGCLASS V64:$Vn, GPR64)>;
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def : Pat<(i64 (bitconvert (v2f32 V64:$Vn))),
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(COPY_TO_REGCLASS V64:$Vn, GPR64)>;
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def : Pat<(i64 (bitconvert (v1f64 V64:$Vn))),
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(COPY_TO_REGCLASS V64:$Vn, GPR64)>;
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def : Pat<(f32 (bitconvert (i32 GPR32:$Xn))), (COPY_TO_REGCLASS GPR32:$Xn,
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FPR32)>;
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def : Pat<(i32 (bitconvert (f32 FPR32:$Xn))), (COPY_TO_REGCLASS FPR32:$Xn,
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GPR32)>;
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def : Pat<(f64 (bitconvert (i64 GPR64:$Xn))), (COPY_TO_REGCLASS GPR64:$Xn,
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FPR64)>;
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def : Pat<(i64 (bitconvert (f64 FPR64:$Xn))), (COPY_TO_REGCLASS FPR64:$Xn,
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GPR64)>;
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def : Pat<(f32 (bitconvert (i32 GPR32:$Xn))),
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(COPY_TO_REGCLASS GPR32:$Xn, FPR32)>;
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def : Pat<(i32 (bitconvert (f32 FPR32:$Xn))),
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(COPY_TO_REGCLASS FPR32:$Xn, GPR32)>;
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def : Pat<(f64 (bitconvert (i64 GPR64:$Xn))),
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(COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
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def : Pat<(i64 (bitconvert (f64 FPR64:$Xn))),
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(COPY_TO_REGCLASS FPR64:$Xn, GPR64)>;
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//===----------------------------------------------------------------------===//
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// Floating point conversion instruction.
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@ -2971,16 +2979,18 @@ def : Pat<(and (vector_extract (v8i16 V128:$Rn), VectorIndexH:$idx),
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defm INS : SIMDIns;
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def : Pat<(v16i8 (scalar_to_vector GPR32:$Rn)),
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(INSvi8gpr (v16i8 (IMPLICIT_DEF)), (i64 0), GPR32:$Rn)>;
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(SUBREG_TO_REG (i32 0),
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(f32 (COPY_TO_REGCLASS GPR32:$Rn, FPR32)), ssub)>;
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def : Pat<(v8i8 (scalar_to_vector GPR32:$Rn)),
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(EXTRACT_SUBREG
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(INSvi8gpr (v16i8 (IMPLICIT_DEF)), (i64 0), GPR32:$Rn), dsub)>;
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(SUBREG_TO_REG (i32 0),
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(f32 (COPY_TO_REGCLASS GPR32:$Rn, FPR32)), ssub)>;
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def : Pat<(v8i16 (scalar_to_vector GPR32:$Rn)),
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(INSvi16gpr (v8i16 (IMPLICIT_DEF)), (i64 0), GPR32:$Rn)>;
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(SUBREG_TO_REG (i32 0),
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(f32 (COPY_TO_REGCLASS GPR32:$Rn, FPR32)), ssub)>;
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def : Pat<(v4i16 (scalar_to_vector GPR32:$Rn)),
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(EXTRACT_SUBREG
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(INSvi16gpr (v8i16 (IMPLICIT_DEF)), (i64 0), GPR32:$Rn), dsub)>;
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(SUBREG_TO_REG (i32 0),
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(f32 (COPY_TO_REGCLASS GPR32:$Rn, FPR32)), ssub)>;
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def : Pat<(v2i32 (scalar_to_vector (i32 FPR32:$Rn))),
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(v2i32 (INSERT_SUBREG (v2i32 (IMPLICIT_DEF)),
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@ -136,6 +136,18 @@ entry:
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ret i64 %vaddv.i
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}
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define <1 x i64> @test_vaddv_u64_to_vec(<2 x i64> %a1) {
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; CHECK-LABEL: test_vaddv_u64_to_vec:
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; CHECK: addp.2d d0, v0
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; CHECK-NOT: fmov
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; CHECK-NOT: ins
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; CHECK: ret
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entry:
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%vaddv.i = tail call i64 @llvm.arm64.neon.uaddv.i64.v2i64(<2 x i64> %a1)
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%vec = insertelement <1 x i64> undef, i64 %vaddv.i, i32 0
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ret <1 x i64> %vec
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}
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define signext i8 @test_vaddvq_s8(<16 x i8> %a1) {
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; CHECK-LABEL: test_vaddvq_s8:
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; CHECK: addv.16b b[[REGNUM:[0-9]+]], v0
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