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ARM: support emission of complex SO expressions

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Support to the IAS was added to actually parse and handle the complex SO
expressions.  However, the object file lowering was not updated to compensate
for the fact that the shift operand may be an absolute expression.

When trying to assemble to an object file, the lowering would fail while
succeeding when emitting purely assembly.  Add an appropriate test.

The test case is inspired by the test case provided by Jiangning Liu who also
brought the issue to light.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203762 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Saleem Abdulrasool 2014-03-13 07:02:41 +00:00
parent b0f12dfab6
commit 0ed4ef85a8
2 changed files with 22 additions and 2 deletions
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15
lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
View File

@ -271,8 +271,19 @@ public:
unsigned getSOImmOpValue(const MCInst &MI, unsigned Op,
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const {
unsigned SoImm = MI.getOperand(Op).getImm();
int SoImmVal = ARM_AM::getSOImmVal(SoImm);
int SoImmVal = -1;
const MCOperand &MO = MI.getOperand(Op);
if (MO.isImm()) {
SoImmVal = ARM_AM::getSOImmVal(MO.getImm());
} else if (MO.isExpr()) {
int64_t Value;
bool Invalid = MO.getExpr()->EvaluateAsAbsolute(Value);
assert(!Invalid && "non-constant expression is not a valid SOImm operand");
assert((Value >= INT32_MIN && Value <= INT32_MAX) &&
"expression must be representable in 32 bits");
SoImmVal = Value;
}
assert(SoImmVal != -1 && "Not a valid so_imm value!");
// Encode rotate_imm.

9
test/MC/ARM/shift-offset-addressing-emission.s Normal file
View File

@ -0,0 +1,9 @@
@ RUN: llvm-mc -triple armv7-elf -filetype obj -o - %s \
@ RUN: | llvm-objdump -disassemble -no-show-raw-insn - | FileCheck %s
cmp r0, #(.L2 - .L1)
.L1:
.L2:
@ CHECK: 0: cmp r0, #0