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ARM NEON two-operand aliases for VQDMULH.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146514 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jim Grosbach 2011-12-13 20:40:37 +00:00
parent e91e7bcadc
commit 0f293de207
3 changed files with 21 additions and 0 deletions
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11
lib/Target/ARM/ARMInstrNEON.td
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@ -5708,6 +5708,17 @@ def : NEONInstAlias<"vext${p}.32 $Vdn, $Vm, $imm",
def : NEONInstAlias<"vext${p}.64 $Vdn, $Vm, $imm",
(VEXTq64 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, imm0_1:$imm, pred:$p)>;
// Two-operand variants for VQDMULH
def : NEONInstAlias<"vqdmulh${p}.s16 $Vdn, $Vm",
(VQDMULHv4i16 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
def : NEONInstAlias<"vqdmulh${p}.s32 $Vdn, $Vm",
(VQDMULHv2i32 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
def : NEONInstAlias<"vqdmulh${p}.s16 $Vdn, $Vm",
(VQDMULHv8i16 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
def : NEONInstAlias<"vqdmulh${p}.s32 $Vdn, $Vm",
(VQDMULHv4i32 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
// 'gas' compatibility aliases for quad-word instructions. Strictly speaking,
// these should restrict to just the Q register variants, but the register
// classes are enough to match correctly regardless, so we keep it simple

2
lib/Target/ARM/ARMInstrVFP.td
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@ -1192,6 +1192,8 @@ def : VFP2MnemonicAlias<"fuitod", "vcvt.f64.u32">;
def : VFP2MnemonicAlias<"fuitos", "vcvt.f32.u32">;
def : VFP2MnemonicAlias<"fsts", "vstr">;
def : VFP2MnemonicAlias<"fstd", "vstr">;
def : VFP2MnemonicAlias<"fmacd", "vmla.f64">;
def : VFP2MnemonicAlias<"fmacs", "vmla.f32">;
def : VFP2InstAlias<"fmstat${p}", (FMSTAT pred:$p)>;
def : VFP2InstAlias<"fadds${p} $Sd, $Sn, $Sm",

8
test/MC/ARM/neon-mul-encoding.s
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@ -51,8 +51,16 @@
vqdmulh.s32 d16, d16, d17
vqdmulh.s16 q8, q8, q9
vqdmulh.s32 q8, q8, q9
vqdmulh.s16 d16, d17
vqdmulh.s32 d16, d17
vqdmulh.s16 q8, q9
vqdmulh.s32 q8, q9
vqdmulh.s16 d11, d2, d3[0]
@ CHECK: vqdmulh.s16 d16, d16, d17 @ encoding: [0xa1,0x0b,0x50,0xf2]
@ CHECK: vqdmulh.s32 d16, d16, d17 @ encoding: [0xa1,0x0b,0x60,0xf2]
@ CHECK: vqdmulh.s16 q8, q8, q9 @ encoding: [0xe2,0x0b,0x50,0xf2]
@ CHECK: vqdmulh.s32 q8, q8, q9 @ encoding: [0xe2,0x0b,0x60,0xf2]
@ CHECK: vqdmulh.s16 d16, d16, d17 @ encoding: [0xa1,0x0b,0x50,0xf2]
@ CHECK: vqdmulh.s32 d16, d16, d17 @ encoding: [0xa1,0x0b,0x60,0xf2]
@ CHECK: vqdmulh.s16 q8, q8, q9 @ encoding: [0xe2,0x0b,0x50,0xf2]