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Simplify the logic in the simple spiller and capitalize some variables

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16609 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2004-09-30 02:59:33 +00:00
parent 5f7d2d45fd
commit 0fc27ccdd3
1 changed files with 88 additions and 84 deletions
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172
lib/CodeGen/VirtRegMap.cpp
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@ -139,37 +139,41 @@ bool SimpleSpiller::runOnMachineFunction(MachineFunction& MF,
// current machine instr, so it should be small. // current machine instr, so it should be small.
std::vector<unsigned> LoadedRegs; std::vector<unsigned> LoadedRegs;
for (MachineFunction::iterator mbbi = MF.begin(), E = MF.end(); for (MachineFunction::iterator MBBI = MF.begin(), E = MF.end();
mbbi != E; ++mbbi) { MBBI != E; ++MBBI) {
DEBUG(std::cerr << mbbi->getBasicBlock()->getName() << ":\n"); DEBUG(std::cerr << MBBI->getBasicBlock()->getName() << ":\n");
for (MachineBasicBlock::iterator mii = mbbi->begin(), MachineBasicBlock &MBB = *MBBI;
mie = mbbi->end(); mii != mie; ++mii) { for (MachineBasicBlock::iterator MII = MBB.begin(),
for (unsigned i = 0, e = mii->getNumOperands(); i != e; ++i) { E = MBB.end(); MII != E; ++MII) {
MachineOperand& mop = mii->getOperand(i); MachineInstr &MI = *MII;
if (mop.isRegister() && mop.getReg() && for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
MRegisterInfo::isVirtualRegister(mop.getReg())) { MachineOperand &MOP = MI.getOperand(i);
unsigned virtReg = mop.getReg(); if (MOP.isRegister() && MOP.getReg() &&
unsigned physReg = VRM.getPhys(virtReg); MRegisterInfo::isVirtualRegister(MOP.getReg())){
if (mop.isUse() && VRM.hasStackSlot(mop.getReg()) && unsigned VirtReg = MOP.getReg();
std::find(LoadedRegs.begin(), LoadedRegs.end(), unsigned PhysReg = VRM.getPhys(VirtReg);
virtReg) == LoadedRegs.end()) { if (VRM.hasStackSlot(VirtReg)) {
MRI.loadRegFromStackSlot(*mbbi, mii, physReg, int StackSlot = VRM.getStackSlot(VirtReg);
VRM.getStackSlot(virtReg));
LoadedRegs.push_back(virtReg);
DEBUG(std::cerr << '\t';
prior(mii)->print(std::cerr, &TM));
++NumLoads;
}
if (mop.isDef() && VRM.hasStackSlot(mop.getReg())) { if (MOP.isUse() &&
MRI.storeRegToStackSlot(*mbbi, next(mii), physReg, std::find(LoadedRegs.begin(), LoadedRegs.end(), VirtReg)
VRM.getStackSlot(virtReg)); == LoadedRegs.end()) {
++NumStores; MRI.loadRegFromStackSlot(MBB, &MI, PhysReg, StackSlot);
LoadedRegs.push_back(VirtReg);
++NumLoads;
DEBUG(std::cerr << '\t'; prior(MII)->print(std::cerr, &TM));
}
if (MOP.isDef()) {
MRI.storeRegToStackSlot(MBB, next(MII), PhysReg,
VRM.getStackSlot(VirtReg));
++NumStores;
}
} }
mii->SetMachineOperandReg(i, physReg); MI.SetMachineOperandReg(i, PhysReg);
} }
} }
DEBUG(std::cerr << '\t'; mii->print(std::cerr, &TM)); DEBUG(std::cerr << '\t'; MI.print(std::cerr, &TM));
LoadedRegs.clear(); LoadedRegs.clear();
} }
} }
@ -199,52 +203,52 @@ namespace {
bool runOnMachineFunction(MachineFunction &MF, const VirtRegMap &VRM); bool runOnMachineFunction(MachineFunction &MF, const VirtRegMap &VRM);
private: private:
void vacateJustPhysReg(MachineBasicBlock& mbb, void vacateJustPhysReg(MachineBasicBlock& MBB,
MachineBasicBlock::iterator mii, MachineBasicBlock::iterator MII,
unsigned physReg); unsigned PhysReg);
void vacatePhysReg(MachineBasicBlock& mbb, void vacatePhysReg(MachineBasicBlock& MBB,
MachineBasicBlock::iterator mii, MachineBasicBlock::iterator MII,
unsigned physReg) { unsigned PhysReg) {
vacateJustPhysReg(mbb, mii, physReg); vacateJustPhysReg(MBB, MII, PhysReg);
for (const unsigned* as = MRI->getAliasSet(physReg); *as; ++as) for (const unsigned* as = MRI->getAliasSet(PhysReg); *as; ++as)
vacateJustPhysReg(mbb, mii, *as); vacateJustPhysReg(MBB, MII, *as);
} }
void handleUse(MachineBasicBlock& mbb, void handleUse(MachineBasicBlock& MBB,
MachineBasicBlock::iterator mii, MachineBasicBlock::iterator MII,
unsigned virtReg, unsigned VirtReg,
unsigned physReg) { unsigned PhysReg) {
// check if we are replacing a previous mapping // check if we are replacing a previous mapping
if (p2vMap_[physReg] != virtReg) { if (p2vMap_[PhysReg] != VirtReg) {
vacatePhysReg(mbb, mii, physReg); vacatePhysReg(MBB, MII, PhysReg);
p2vMap_[physReg] = virtReg; p2vMap_[PhysReg] = VirtReg;
// load if necessary // load if necessary
if (VRM->hasStackSlot(virtReg)) { if (VRM->hasStackSlot(VirtReg)) {
MRI->loadRegFromStackSlot(mbb, mii, physReg, MRI->loadRegFromStackSlot(MBB, MII, PhysReg,
VRM->getStackSlot(virtReg)); VRM->getStackSlot(VirtReg));
++NumLoads; ++NumLoads;
DEBUG(std::cerr << "added: "; DEBUG(std::cerr << "added: ";
prior(mii)->print(std::cerr, TM)); prior(MII)->print(std::cerr, TM));
lastDef_[virtReg] = mii; lastDef_[VirtReg] = MII;
} }
} }
} }
void handleDef(MachineBasicBlock& mbb, void handleDef(MachineBasicBlock& MBB,
MachineBasicBlock::iterator mii, MachineBasicBlock::iterator MII,
unsigned virtReg, unsigned VirtReg,
unsigned physReg) { unsigned PhysReg) {
// check if we are replacing a previous mapping // check if we are replacing a previous mapping
if (p2vMap_[physReg] != virtReg) if (p2vMap_[PhysReg] != VirtReg)
vacatePhysReg(mbb, mii, physReg); vacatePhysReg(MBB, MII, PhysReg);
p2vMap_[physReg] = virtReg; p2vMap_[PhysReg] = VirtReg;
dirty_[physReg] = true; dirty_[PhysReg] = true;
lastDef_[virtReg] = mii; lastDef_[VirtReg] = MII;
} }
void eliminateVirtRegsInMbb(MachineBasicBlock& mbb); void eliminateVirtRegsInMBB(MachineBasicBlock& MBB);
}; };
} }
@ -262,11 +266,11 @@ bool LocalSpiller::runOnMachineFunction(MachineFunction &mf,
DEBUG(std::cerr << "********** Function: " DEBUG(std::cerr << "********** Function: "
<< MF->getFunction()->getName() << '\n'); << MF->getFunction()->getName() << '\n');
for (MachineFunction::iterator mbbi = MF->begin(), for (MachineFunction::iterator MBB = MF->begin(), E = MF->end();
mbbe = MF->end(); mbbi != mbbe; ++mbbi) { MBB != E; ++MBB) {
lastDef_.grow(MF->getSSARegMap()->getLastVirtReg()); lastDef_.grow(MF->getSSARegMap()->getLastVirtReg());
DEBUG(std::cerr << mbbi->getBasicBlock()->getName() << ":\n"); DEBUG(std::cerr << MBB->getBasicBlock()->getName() << ":\n");
eliminateVirtRegsInMbb(*mbbi); eliminateVirtRegsInMBB(*MBB);
// clear map, dirty flag and last ref // clear map, dirty flag and last ref
p2vMap_.assign(p2vMap_.size(), 0); p2vMap_.assign(p2vMap_.size(), 0);
dirty_.assign(dirty_.size(), false); dirty_.assign(dirty_.size(), false);
@ -275,31 +279,31 @@ bool LocalSpiller::runOnMachineFunction(MachineFunction &mf,
return true; return true;
} }
void LocalSpiller::vacateJustPhysReg(MachineBasicBlock& mbb, void LocalSpiller::vacateJustPhysReg(MachineBasicBlock& MBB,
MachineBasicBlock::iterator mii, MachineBasicBlock::iterator MII,
unsigned physReg) { unsigned PhysReg) {
unsigned virtReg = p2vMap_[physReg]; unsigned VirtReg = p2vMap_[PhysReg];
if (dirty_[physReg] && VRM->hasStackSlot(virtReg)) { if (dirty_[PhysReg] && VRM->hasStackSlot(VirtReg)) {
assert(lastDef_[virtReg] && "virtual register is mapped " assert(lastDef_[VirtReg] && "virtual register is mapped "
"to a register and but was not defined!"); "to a register and but was not defined!");
MachineBasicBlock::iterator lastDef = lastDef_[virtReg]; MachineBasicBlock::iterator lastDef = lastDef_[VirtReg];
MachineBasicBlock::iterator nextLastRef = next(lastDef); MachineBasicBlock::iterator nextLastRef = next(lastDef);
MRI->storeRegToStackSlot(*lastDef->getParent(), MRI->storeRegToStackSlot(*lastDef->getParent(),
nextLastRef, nextLastRef,
physReg, PhysReg,
VRM->getStackSlot(virtReg)); VRM->getStackSlot(VirtReg));
++NumStores; ++NumStores;
DEBUG(std::cerr << "added: "; DEBUG(std::cerr << "added: ";
prior(nextLastRef)->print(std::cerr, TM); prior(nextLastRef)->print(std::cerr, TM);
std::cerr << "after: "; std::cerr << "after: ";
lastDef->print(std::cerr, TM)); lastDef->print(std::cerr, TM));
lastDef_[virtReg] = 0; lastDef_[VirtReg] = 0;
} }
p2vMap_[physReg] = 0; p2vMap_[PhysReg] = 0;
dirty_[physReg] = false; dirty_[PhysReg] = false;
} }
void LocalSpiller::eliminateVirtRegsInMbb(MachineBasicBlock &MBB) { void LocalSpiller::eliminateVirtRegsInMBB(MachineBasicBlock &MBB) {
for (MachineBasicBlock::iterator MI = MBB.begin(), E = MBB.end(); for (MachineBasicBlock::iterator MI = MBB.begin(), E = MBB.end();
MI != E; ++MI) { MI != E; ++MI) {
@ -317,14 +321,14 @@ void LocalSpiller::eliminateVirtRegsInMbb(MachineBasicBlock &MBB) {
MachineOperand& op = MI->getOperand(i); MachineOperand& op = MI->getOperand(i);
if (op.isRegister() && op.getReg() && op.isUse() && if (op.isRegister() && op.getReg() && op.isUse() &&
MRegisterInfo::isVirtualRegister(op.getReg())) { MRegisterInfo::isVirtualRegister(op.getReg())) {
unsigned virtReg = op.getReg(); unsigned VirtReg = op.getReg();
unsigned physReg = VRM->getPhys(virtReg); unsigned PhysReg = VRM->getPhys(VirtReg);
handleUse(MBB, MI, virtReg, physReg); handleUse(MBB, MI, VirtReg, PhysReg);
MI->SetMachineOperandReg(i, physReg); MI->SetMachineOperandReg(i, PhysReg);
// mark as dirty if this is def&use // mark as dirty if this is def&use
if (op.isDef()) { if (op.isDef()) {
dirty_[physReg] = true; dirty_[PhysReg] = true;
lastDef_[virtReg] = MI; lastDef_[VirtReg] = MI;
} }
} }
} }
@ -350,9 +354,9 @@ void LocalSpiller::eliminateVirtRegsInMbb(MachineBasicBlock &MBB) {
if (MRegisterInfo::isPhysicalRegister(op.getReg())) if (MRegisterInfo::isPhysicalRegister(op.getReg()))
vacatePhysReg(MBB, MI, op.getReg()); vacatePhysReg(MBB, MI, op.getReg());
else { else {
unsigned physReg = VRM->getPhys(op.getReg()); unsigned PhysReg = VRM->getPhys(op.getReg());
handleDef(MBB, MI, op.getReg(), physReg); handleDef(MBB, MI, op.getReg(), PhysReg);
MI->SetMachineOperandReg(i, physReg); MI->SetMachineOperandReg(i, PhysReg);
} }
} }