6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-11-03 14:21:30 +00:00
Code Issues Projects Releases Wiki Activity

remove dead code

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24965 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner
2005-12-22 21:16:08 +00:00
parent cec26fc3bf
commit 0fcd40f501
5 changed files with 0 additions and 37 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
View File

@@ -589,12 +589,6 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
AddLegalizedOperand(Op.getValue(0), Result); AddLegalizedOperand(Op.getValue(0), Result);
AddLegalizedOperand(Op.getValue(1), Result.getValue(1)); AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
return Result.getValue(Op.ResNo); return Result.getValue(Op.ResNo);
case ISD::ImplicitDef:
Tmp1 = LegalizeOp(Node->getOperand(0));
if (Tmp1 != Node->getOperand(0))
Result = DAG.getNode(ISD::ImplicitDef, MVT::Other,
Tmp1, Node->getOperand(1));
break;
case ISD::UNDEF: { case ISD::UNDEF: {
MVT::ValueType VT = Op.getValueType(); MVT::ValueType VT = Op.getValueType();
switch (TLI.getOperationAction(ISD::UNDEF, VT)) { switch (TLI.getOperationAction(ISD::UNDEF, VT)) {

1
lib/CodeGen/SelectionDAG/SelectionDAG.cpp
View File

@@ -1874,7 +1874,6 @@ const char *SDNode::getOperationName(const SelectionDAG *G) const {
case ISD::TargetConstantPool: return "TargetConstantPool"; case ISD::TargetConstantPool: return "TargetConstantPool";
case ISD::CopyToReg: return "CopyToReg"; case ISD::CopyToReg: return "CopyToReg";
case ISD::CopyFromReg: return "CopyFromReg"; case ISD::CopyFromReg: return "CopyFromReg";
case ISD::ImplicitDef: return "ImplicitDef";
case ISD::UNDEF: return "undef"; case ISD::UNDEF: return "undef";
// Unary operators // Unary operators

13
lib/Target/Alpha/AlphaISelPattern.cpp
View File

@@ -1600,19 +1600,6 @@ void AlphaISel::Select(SDOperand N) {
return; return;
} }
case ISD::ImplicitDef:
++count_ins;
Select(N.getOperand(0));
switch(N.getValueType()) {
case MVT::f32: Opc = Alpha::IDEF_F32; break;
case MVT::f64: Opc = Alpha::IDEF_F64; break;
case MVT::i64: Opc = Alpha::IDEF_I; break;
default: assert(0 && "should have been legalized");
};
BuildMI(BB, Opc, 0,
cast<RegisterSDNode>(N.getOperand(1))->getReg());
return;
case ISD::EntryToken: return; // Noop case ISD::EntryToken: return; // Noop
case ISD::TokenFactor: case ISD::TokenFactor:

7
lib/Target/IA64/IA64ISelPattern.cpp
View File

@@ -2281,13 +2281,6 @@ void ISel::Select(SDOperand N) {
return; return;
} }
case ISD::ImplicitDef: {
Select(N.getOperand(0));
BuildMI(BB, IA64::IDEF, 0,
cast<RegisterSDNode>(N.getOperand(1))->getReg());
return;
}
case ISD::BRCOND: { case ISD::BRCOND: {
MachineBasicBlock *Dest = MachineBasicBlock *Dest =
cast<BasicBlockSDNode>(N.getOperand(2))->getBasicBlock(); cast<BasicBlockSDNode>(N.getOperand(2))->getBasicBlock();

10
lib/Target/PowerPC/PPCISelPattern.cpp
View File

@@ -1601,16 +1601,6 @@ void ISel::Select(SDOperand N) {
BuildMI(BB, PPC::OR4, 2, Tmp2).addReg(Tmp1).addReg(Tmp1); BuildMI(BB, PPC::OR4, 2, Tmp2).addReg(Tmp1).addReg(Tmp1);
} }
return; return;
case ISD::ImplicitDef:
Select(N.getOperand(0));
Tmp1 = cast<RegisterSDNode>(N.getOperand(1))->getReg();
if (N.getOperand(1).getValueType() == MVT::i32)
BuildMI(BB, PPC::IMPLICIT_DEF_GPR, 0, Tmp1);
else if (N.getOperand(1).getValueType() == MVT::f32)
BuildMI(BB, PPC::IMPLICIT_DEF_F4, 0, Tmp1);
else
BuildMI(BB, PPC::IMPLICIT_DEF_F8, 0, Tmp1);
return;
case ISD::RET: case ISD::RET:
switch (N.getNumOperands()) { switch (N.getNumOperands()) {
default: default: