Add support for generating reg+reg (indexed) pre-inc loads on PPC.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158823 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Hal Finkel
2012-06-20 15:43:03 +00:00
parent d65e463ff9
commit 0fcdd8b2cc
5 changed files with 155 additions and 10 deletions

View File

@@ -0,0 +1,49 @@
target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64"
target triple = "powerpc64-unknown-linux-gnu"
; RUN: llc < %s | FileCheck %s
define fastcc void @allocateSpace() nounwind {
entry:
%0 = load i8** undef, align 8, !tbaa !0
br i1 undef, label %return, label %lor.lhs.false
lor.lhs.false: ; preds = %entry
br i1 undef, label %if.end7, label %return
if.end7: ; preds = %lor.lhs.false
br i1 undef, label %if.then15, label %if.end71
if.then15: ; preds = %if.end7
br label %while.cond
while.cond: ; preds = %while.body, %if.then15
%idxprom17 = sext i32 0 to i64
%arrayidx18 = getelementptr inbounds i8* %0, i64 %idxprom17
%or = or i32 undef, undef
br i1 false, label %if.end71, label %while.body
while.body: ; preds = %while.cond
br i1 undef, label %while.cond, label %if.then45
if.then45: ; preds = %while.body
%idxprom48139 = zext i32 %or to i64
%arrayidx49 = getelementptr inbounds i8* %0, i64 %idxprom48139
%1 = bitcast i8* %arrayidx49 to i16*
%2 = bitcast i8* %arrayidx18 to i16*
%3 = load i16* %1, align 1
store i16 %3, i16* %2, align 1
br label %return
if.end71: ; preds = %while.cond, %if.end7
unreachable
return: ; preds = %if.then45, %lor.lhs.false, %entry
ret void
; CHECK: @allocateSpace
; CHECK: lbzux
}
!0 = metadata !{metadata !"any pointer", metadata !1}
!1 = metadata !{metadata !"omnipotent char", metadata !2}
!2 = metadata !{metadata !"Simple C/C++ TBAA"}