6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-08-12 17:25:49 +00:00
Code Issues Projects Releases Wiki Activity

Rename all the M_* flags to be namespace qualified enums, and switch

Browse Source 
all clients over to using predicates instead of these flags directly.
These are now private values which are only to be used to statically
initialize the tables.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45692 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner
2008-01-07 06:42:05 +00:00
parent c17d69fa1e
commit 0ff23966fe
6 changed files with 91 additions and 82 deletions
Download Patch File Download Diff File Expand all files Collapse all files

115
include/llvm/Target/TargetInstrInfo.h
View File

@@ -22,8 +22,6 @@
namespace llvm { namespace llvm {
class MachineInstr;
class TargetMachine;
class TargetRegisterClass; class TargetRegisterClass;
class LiveVariables; class LiveVariables;
class CalleeSavedInfo; class CalleeSavedInfo;
@@ -46,9 +44,9 @@ namespace TOI {
/// private, all access should go through the TargetOperandInfo accessors. /// private, all access should go through the TargetOperandInfo accessors.
/// See the accessors for a description of what these are. /// See the accessors for a description of what these are.
enum OperandFlags { enum OperandFlags {
LookupPtrRegClass = 1 << 0, LookupPtrRegClass = 0,
Predicate = 1 << 1, Predicate,
OptionalDef = 1 << 2 OptionalDef
}; };
} }
@@ -68,15 +66,15 @@ public:
/// isLookupPtrRegClass - Set if this operand is a pointer value and it /// isLookupPtrRegClass - Set if this operand is a pointer value and it
/// requires a callback to look up its register class. /// requires a callback to look up its register class.
bool isLookupPtrRegClass() const { return Flags & TOI::LookupPtrRegClass; } bool isLookupPtrRegClass() const { return Flags&(1 <<TOI::LookupPtrRegClass);}
/// isPredicate - Set if this is one of the operands that made up of /// isPredicate - Set if this is one of the operands that made up of
/// the predicate operand that controls an isPredicable() instruction. /// the predicate operand that controls an isPredicable() instruction.
bool isPredicate() const { return Flags & TOI::Predicate; } bool isPredicate() const { return Flags & (1 << TOI::Predicate); }
/// isOptionalDef - Set if this operand is a optional def. /// isOptionalDef - Set if this operand is a optional def.
/// ///
bool isOptionalDef() const { return Flags & TOI::OptionalDef; } bool isOptionalDef() const { return Flags & (1 << TOI::OptionalDef); }
}; };
@@ -84,29 +82,40 @@ public:
// Machine Instruction Flags and Description // Machine Instruction Flags and Description
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
const unsigned M_BRANCH_FLAG = 1 << 0; /// TargetInstrDescriptor flags - These should be considered private to the
const unsigned M_CALL_FLAG = 1 << 1; /// implementation of the TargetInstrDescriptor class. Clients should use the
const unsigned M_RET_FLAG = 1 << 2; /// predicate methods on TargetInstrDescriptor, not use these directly. These
const unsigned M_BARRIER_FLAG = 1 << 3; /// all correspond to bitfields in the TargetInstrDescriptor::Flags field.
const unsigned M_DELAY_SLOT_FLAG = 1 << 4; namespace TID {
const unsigned M_SIMPLE_LOAD_FLAG = 1 << 5; enum {
const unsigned M_MAY_STORE_FLAG = 1 << 6; Variadic = 0,
const unsigned M_INDIRECT_FLAG = 1 << 7; HasOptionalDef,
const unsigned M_IMPLICIT_DEF_FLAG = 1 << 8; Return,
const unsigned M_CONVERTIBLE_TO_3_ADDR = 1 << 9; Call,
const unsigned M_COMMUTABLE = 1 << 10; ImplicitDef,
const unsigned M_TERMINATOR_FLAG = 1 << 11; Barrier,
const unsigned M_USES_CUSTOM_DAG_SCHED_INSERTION = 1 << 12; Terminator,
const unsigned M_VARIADIC = 1 << 13; Branch,
const unsigned M_PREDICABLE = 1 << 14; IndirectBranch,
const unsigned M_REMATERIALIZIBLE = 1 << 15; Predicable,
const unsigned M_NOT_DUPLICABLE = 1 << 16; NotDuplicable,
const unsigned M_HAS_OPTIONAL_DEF = 1 << 17; DelaySlot,
const unsigned M_NEVER_HAS_SIDE_EFFECTS = 1 << 18; SimpleLoad,
const unsigned M_MAY_HAVE_SIDE_EFFECTS = 1 << 19; MayStore,
NeverHasSideEffects,
MayHaveSideEffects,
Commutable,
ConvertibleTo3Addr,
UsesCustomDAGSchedInserter,
Rematerializable
};
}
/// TargetInstrDescriptor - Describe properties that are true of each
/// instruction in the target description file. This captures information about
/// side effects, register use and many other things. There is one instance of
/// this struct for each target instruction class, and the MachineInstr class
/// points to this struct directly to describe itself.
class TargetInstrDescriptor { class TargetInstrDescriptor {
public: public:
unsigned short Opcode; // The opcode number. unsigned short Opcode; // The opcode number.
@@ -118,7 +127,7 @@ public:
unsigned TSFlags; // Target Specific Flag values unsigned TSFlags; // Target Specific Flag values
const unsigned *ImplicitUses; // Registers implicitly read by this instr const unsigned *ImplicitUses; // Registers implicitly read by this instr
const unsigned *ImplicitDefs; // Registers implicitly defined by this instr const unsigned *ImplicitDefs; // Registers implicitly defined by this instr
const TargetOperandInfo *OpInfo; // 'numOperands' entries about operands. const TargetOperandInfo *OpInfo; // 'NumOperands' entries about operands.
/// getOperandConstraint - Returns the value of the specific constraint if /// getOperandConstraint - Returns the value of the specific constraint if
/// it is set. Returns -1 if it is not set. /// it is set. Returns -1 if it is not set.
@@ -165,13 +174,13 @@ public:
/// operands but before the implicit definitions and uses (if any are /// operands but before the implicit definitions and uses (if any are
/// present). /// present).
bool isVariadic() const { bool isVariadic() const {
return Flags & M_VARIADIC; return Flags & (1 << TID::Variadic);
} }
/// hasOptionalDef - Set if this instruction has an optional definition, e.g. /// hasOptionalDef - Set if this instruction has an optional definition, e.g.
/// ARM instructions which can set condition code if 's' bit is set. /// ARM instructions which can set condition code if 's' bit is set.
bool hasOptionalDef() const { bool hasOptionalDef() const {
return Flags & M_HAS_OPTIONAL_DEF; return Flags & (1 << TID::HasOptionalDef);
} }
/// getImplicitUses - Return a list of machine operands that are potentially /// getImplicitUses - Return a list of machine operands that are potentially
@@ -211,25 +220,25 @@ public:
} }
bool isReturn() const { bool isReturn() const {
return Flags & M_RET_FLAG; return Flags & (1 << TID::Return);
} }
bool isCall() const { bool isCall() const {
return Flags & M_CALL_FLAG; return Flags & (1 << TID::Call);
} }
/// isImplicitDef - Return true if this is an "IMPLICIT_DEF" instruction, /// isImplicitDef - Return true if this is an "IMPLICIT_DEF" instruction,
/// which defines a register to an unspecified value. These basically /// which defines a register to an unspecified value. These basically
/// correspond to x = undef. /// correspond to x = undef.
bool isImplicitDef() const { bool isImplicitDef() const {
return Flags & M_IMPLICIT_DEF_FLAG; return Flags & (1 << TID::ImplicitDef);
} }
/// isBarrier - Returns true if the specified instruction stops control flow /// isBarrier - Returns true if the specified instruction stops control flow
/// from executing the instruction immediately following it. Examples include /// from executing the instruction immediately following it. Examples include
/// unconditional branches and return instructions. /// unconditional branches and return instructions.
bool isBarrier() const { bool isBarrier() const {
return Flags & M_BARRIER_FLAG; return Flags & (1 << TID::Barrier);
} }
/// isTerminator - Returns true if this instruction part of the terminator for /// isTerminator - Returns true if this instruction part of the terminator for
@@ -239,7 +248,7 @@ public:
/// Various passes use this to insert code into the bottom of a basic block, /// Various passes use this to insert code into the bottom of a basic block,
/// but before control flow occurs. /// but before control flow occurs.
bool isTerminator() const { bool isTerminator() const {
return Flags & M_TERMINATOR_FLAG; return Flags & (1 << TID::Terminator);
} }
/// isBranch - Returns true if this is a conditional, unconditional, or /// isBranch - Returns true if this is a conditional, unconditional, or
@@ -247,13 +256,13 @@ public:
/// these cases, and the TargetInstrInfo::AnalyzeBranch method can be used to /// these cases, and the TargetInstrInfo::AnalyzeBranch method can be used to
/// get more information. /// get more information.
bool isBranch() const { bool isBranch() const {
return Flags & M_BRANCH_FLAG; return Flags & (1 << TID::Branch);
} }
/// isIndirectBranch - Return true if this is an indirect branch, such as a /// isIndirectBranch - Return true if this is an indirect branch, such as a
/// branch through a register. /// branch through a register.
bool isIndirectBranch() const { bool isIndirectBranch() const {
return Flags & M_INDIRECT_FLAG; return Flags & (1 << TID::IndirectBranch);
} }
/// isConditionalBranch - Return true if this is a branch which may fall /// isConditionalBranch - Return true if this is a branch which may fall
@@ -277,20 +286,20 @@ public:
/// values. There are various methods in TargetInstrInfo that can be used to /// values. There are various methods in TargetInstrInfo that can be used to
/// control and modify the predicate in this instruction. /// control and modify the predicate in this instruction.
bool isPredicable() const { bool isPredicable() const {
return Flags & M_PREDICABLE; return Flags & (1 << TID::Predicable);
} }
/// isNotDuplicable - Return true if this instruction cannot be safely /// isNotDuplicable - Return true if this instruction cannot be safely
/// duplicated. For example, if the instruction has a unique labels attached /// duplicated. For example, if the instruction has a unique labels attached
/// to it, duplicating it would cause multiple definition errors. /// to it, duplicating it would cause multiple definition errors.
bool isNotDuplicable() const { bool isNotDuplicable() const {
return Flags & M_NOT_DUPLICABLE; return Flags & (1 << TID::NotDuplicable);
} }
/// hasDelaySlot - Returns true if the specified instruction has a delay slot /// hasDelaySlot - Returns true if the specified instruction has a delay slot
/// which must be filled by the code generator. /// which must be filled by the code generator.
bool hasDelaySlot() const { bool hasDelaySlot() const {
return Flags & M_DELAY_SLOT_FLAG; return Flags & (1 << TID::DelaySlot);
} }
/// isSimpleLoad - Return true for instructions that are simple loads from /// isSimpleLoad - Return true for instructions that are simple loads from
@@ -299,7 +308,7 @@ public:
/// Instructions that return a value loaded from memory and then modified in /// Instructions that return a value loaded from memory and then modified in
/// some way should not return true for this. /// some way should not return true for this.
bool isSimpleLoad() const { bool isSimpleLoad() const {
return Flags & M_SIMPLE_LOAD_FLAG; return Flags & (1 << TID::SimpleLoad);
} }
//===--------------------------------------------------------------------===// //===--------------------------------------------------------------------===//
@@ -311,7 +320,7 @@ public:
/// instructions, they may store a modified value based on their operands, or /// instructions, they may store a modified value based on their operands, or
/// may not actually modify anything, for example. /// may not actually modify anything, for example.
bool mayStore() const { bool mayStore() const {
return Flags & M_MAY_STORE_FLAG; return Flags & (1 << TID::MayStore);
} }
// TODO: mayLoad. // TODO: mayLoad.
@@ -333,7 +342,7 @@ public:
/// TargetInstrInfo::hasUnmodelledSideEffects method, which handles analysis /// TargetInstrInfo::hasUnmodelledSideEffects method, which handles analysis
/// of the machine instruction. /// of the machine instruction.
bool hasNoSideEffects() const { bool hasNoSideEffects() const {
return Flags & M_NEVER_HAS_SIDE_EFFECTS; return Flags & (1 << TID::NeverHasSideEffects);
} }
/// hasConditionalSideEffects - Return true if some instances of this /// hasConditionalSideEffects - Return true if some instances of this
@@ -346,14 +355,14 @@ public:
/// TargetInstrInfo::hasUnmodelledSideEffects method, which handles analysis /// TargetInstrInfo::hasUnmodelledSideEffects method, which handles analysis
/// of the machine instruction. /// of the machine instruction.
bool hasConditionalSideEffects() const { bool hasConditionalSideEffects() const {
return Flags & M_MAY_HAVE_SIDE_EFFECTS; return Flags & (1 << TID::MayHaveSideEffects);
} }
//===--------------------------------------------------------------------===// //===--------------------------------------------------------------------===//
// Flags that indicate whether an instruction can be modified by a method. // Flags that indicate whether an instruction can be modified by a method.
//===--------------------------------------------------------------------===// //===--------------------------------------------------------------------===//
/// isCommutableInstr - Return true if this may be a 2- or 3-address /// isCommutable - Return true if this may be a 2- or 3-address
/// instruction (of the form "X = op Y, Z, ..."), which produces the same /// instruction (of the form "X = op Y, Z, ..."), which produces the same
/// result if Y and Z are exchanged. If this flag is set, then the /// result if Y and Z are exchanged. If this flag is set, then the
/// TargetInstrInfo::commuteInstruction method may be used to hack on the /// TargetInstrInfo::commuteInstruction method may be used to hack on the
@@ -363,8 +372,8 @@ public:
/// sometimes. In these cases, the call to commuteInstruction will fail. /// sometimes. In these cases, the call to commuteInstruction will fail.
/// Also note that some instructions require non-trivial modification to /// Also note that some instructions require non-trivial modification to
/// commute them. /// commute them.
bool isCommutableInstr() const { bool isCommutable() const {
return Flags & M_COMMUTABLE; return Flags & (1 << TID::Commutable);
} }
/// isConvertibleTo3Addr - Return true if this is a 2-address instruction /// isConvertibleTo3Addr - Return true if this is a 2-address instruction
@@ -382,7 +391,7 @@ public:
/// instruction (e.g. shl reg, 4 on x86). /// instruction (e.g. shl reg, 4 on x86).
/// ///
bool isConvertibleTo3Addr() const { bool isConvertibleTo3Addr() const {
return Flags & M_CONVERTIBLE_TO_3_ADDR; return Flags & (1 << TID::ConvertibleTo3Addr);
} }
/// usesCustomDAGSchedInsertionHook - Return true if this instruction requires /// usesCustomDAGSchedInsertionHook - Return true if this instruction requires
@@ -394,7 +403,7 @@ public:
/// If this is true, the TargetLoweringInfo::InsertAtEndOfBasicBlock method /// If this is true, the TargetLoweringInfo::InsertAtEndOfBasicBlock method
/// is used to insert this into the MachineBasicBlock. /// is used to insert this into the MachineBasicBlock.
bool usesCustomDAGSchedInsertionHook() const { bool usesCustomDAGSchedInsertionHook() const {
return Flags & M_USES_CUSTOM_DAG_SCHED_INSERTION; return Flags & (1 << TID::UsesCustomDAGSchedInserter);
} }
/// isRematerializable - Returns true if this instruction is a candidate for /// isRematerializable - Returns true if this instruction is a candidate for
@@ -402,7 +411,7 @@ public:
/// flag is set, the isReallyTriviallyReMaterializable() method is called to /// flag is set, the isReallyTriviallyReMaterializable() method is called to
/// verify the instruction is really rematable. /// verify the instruction is really rematable.
bool isRematerializable() const { bool isRematerializable() const {
return Flags & M_REMATERIALIZIBLE; return Flags & (1 << TID::Rematerializable);
} }
}; };

2
lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
View File

@@ -155,7 +155,7 @@ void ScheduleDAG::BuildSchedUnits() {
break; break;
} }
} }
if (TID.Flags & M_COMMUTABLE) if (TID.isCommutable())
SU->isCommutable = true; SU->isCommutable = true;
} }

2
lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
View File

@@ -437,7 +437,7 @@ SUnit *ScheduleDAGRRList::CopyAndMoveSuccessors(SUnit *SU) {
break; break;
} }
} }
if (TID->Flags & M_COMMUTABLE) if (TID->isCommutable())
NewSU->isCommutable = true; NewSU->isCommutable = true;
// FIXME: Calculate height / depth and propagate the changes? // FIXME: Calculate height / depth and propagate the changes?
NewSU->Depth = SU->Depth; NewSU->Depth = SU->Depth;

2
lib/CodeGen/TwoAddressInstructionPass.cpp
View File

@@ -144,7 +144,7 @@ bool TwoAddressInstructionPass::runOnMachineFunction(MachineFunction &MF) {
// so, swap the B and C operands. This makes the live ranges of A // so, swap the B and C operands. This makes the live ranges of A
// and C joinable. // and C joinable.
// FIXME: This code also works for A := B op C instructions. // FIXME: This code also works for A := B op C instructions.
if ((TID->Flags & M_COMMUTABLE) && mi->getNumOperands() >= 3) { if (TID->isCommutable() && mi->getNumOperands() >= 3) {
assert(mi->getOperand(3-si).isRegister() && assert(mi->getOperand(3-si).isRegister() &&
"Not a proper commutative instruction!"); "Not a proper commutative instruction!");
unsigned regC = mi->getOperand(3-si).getReg(); unsigned regC = mi->getOperand(3-si).getReg();

2
lib/Target/ARM/ARMInstrInfo.cpp
View File

@@ -838,7 +838,7 @@ ARMInstrInfo::SubsumesPredicate(const std::vector<MachineOperand> &Pred1,
bool ARMInstrInfo::DefinesPredicate(MachineInstr *MI, bool ARMInstrInfo::DefinesPredicate(MachineInstr *MI,
std::vector<MachineOperand> &Pred) const { std::vector<MachineOperand> &Pred) const {
const TargetInstrDescriptor *TID = MI->getDesc(); const TargetInstrDescriptor *TID = MI->getDesc();
if (!TID->ImplicitDefs && (TID->Flags & M_HAS_OPTIONAL_DEF) == 0) if (!TID->getImplicitDefs() && !TID->hasOptionalDef())
return false; return false;
bool Found = false; bool Found = false;

50
utils/TableGen/InstrInfoEmitter.cpp
View File

@@ -94,17 +94,17 @@ InstrInfoEmitter::GetOperandInfo(const CodeGenInstruction &Inst) {
// Ptr value whose register class is resolved via callback. // Ptr value whose register class is resolved via callback.
if (OpR->getName() == "ptr_rc") if (OpR->getName() == "ptr_rc")
Res += "|TOI::LookupPtrRegClass"; Res += "|(1<<TOI::LookupPtrRegClass)";
// Predicate operands. Check to see if the original unexpanded operand // Predicate operands. Check to see if the original unexpanded operand
// was of type PredicateOperand. // was of type PredicateOperand.
if (Inst.OperandList[i].Rec->isSubClassOf("PredicateOperand")) if (Inst.OperandList[i].Rec->isSubClassOf("PredicateOperand"))
Res += "|TOI::Predicate"; Res += "|(1<<TOI::Predicate)";
// Optional def operands. Check to see if the original unexpanded operand // Optional def operands. Check to see if the original unexpanded operand
// was of type OptionalDefOperand. // was of type OptionalDefOperand.
if (Inst.OperandList[i].Rec->isSubClassOf("OptionalDefOperand")) if (Inst.OperandList[i].Rec->isSubClassOf("OptionalDefOperand"))
Res += "|TOI::OptionalDef"; Res += "|(1<<TOI::OptionalDef)";
// Fill in constraint info. // Fill in constraint info.
Res += ", " + Inst.OperandList[i].Constraints[j]; Res += ", " + Inst.OperandList[i].Constraints[j];
@@ -281,8 +281,8 @@ void InstrInfoEmitter::emitRecord(const CodeGenInstruction &Inst, unsigned Num,
const OperandInfoMapTy &OpInfo, const OperandInfoMapTy &OpInfo,
std::ostream &OS) { std::ostream &OS) {
// Determine properties of the instruction from its pattern. // Determine properties of the instruction from its pattern.
bool mayStore, isLoad, NeverHasSideEffects; bool mayStore, isSimpleLoad, NeverHasSideEffects;
InferFromPattern(Inst, mayStore, isLoad, NeverHasSideEffects); InferFromPattern(Inst, mayStore, isSimpleLoad, NeverHasSideEffects);
if (NeverHasSideEffects && Inst.mayHaveSideEffects) { if (NeverHasSideEffects && Inst.mayHaveSideEffects) {
std::cerr << "error: Instruction '" << Inst.TheDef->getName() std::cerr << "error: Instruction '" << Inst.TheDef->getName()
@@ -302,27 +302,27 @@ void InstrInfoEmitter::emitRecord(const CodeGenInstruction &Inst, unsigned Num,
<< ",\t\"" << Inst.TheDef->getName() << "\", 0"; << ",\t\"" << Inst.TheDef->getName() << "\", 0";
// Emit all of the target indepedent flags... // Emit all of the target indepedent flags...
if (Inst.isReturn) OS << "|M_RET_FLAG"; if (Inst.isReturn) OS << "|(1<<TID::Return)";
if (Inst.isBranch) OS << "|M_BRANCH_FLAG"; if (Inst.isBranch) OS << "|(1<<TID::Branch)";
if (Inst.isIndirectBranch) OS << "|M_INDIRECT_FLAG"; if (Inst.isIndirectBranch) OS << "|(1<<TID::IndirectBranch)";
if (Inst.isBarrier) OS << "|M_BARRIER_FLAG"; if (Inst.isBarrier) OS << "|(1<<TID::Barrier)";
if (Inst.hasDelaySlot) OS << "|M_DELAY_SLOT_FLAG"; if (Inst.hasDelaySlot) OS << "|(1<<TID::DelaySlot)";
if (Inst.isCall) OS << "|M_CALL_FLAG"; if (Inst.isCall) OS << "|(1<<TID::Call)";
if (isLoad) OS << "|M_SIMPLE_LOAD_FLAG"; if (isSimpleLoad) OS << "|(1<<TID::SimpleLoad)";
if (mayStore) OS << "|M_MAY_STORE_FLAG"; if (mayStore) OS << "|(1<<TID::MayStore)";
if (Inst.isImplicitDef)OS << "|M_IMPLICIT_DEF_FLAG"; if (Inst.isImplicitDef)OS << "|(1<<TID::ImplicitDef)";
if (Inst.isPredicable) OS << "|M_PREDICABLE"; if (Inst.isPredicable) OS << "|(1<<TID::Predicable)";
if (Inst.isConvertibleToThreeAddress) OS << "|M_CONVERTIBLE_TO_3_ADDR"; if (Inst.isConvertibleToThreeAddress) OS << "|(1<<TID::ConvertibleTo3Addr)";
if (Inst.isCommutable) OS << "|M_COMMUTABLE"; if (Inst.isCommutable) OS << "|(1<<TID::Commutable)";
if (Inst.isTerminator) OS << "|M_TERMINATOR_FLAG"; if (Inst.isTerminator) OS << "|(1<<TID::Terminator)";
if (Inst.isReMaterializable) OS << "|M_REMATERIALIZIBLE"; if (Inst.isReMaterializable) OS << "|(1<<TID::Rematerializable)";
if (Inst.isNotDuplicable) OS << "|M_NOT_DUPLICABLE"; if (Inst.isNotDuplicable) OS << "|(1<<TID::NotDuplicable)";
if (Inst.hasOptionalDef) OS << "|M_HAS_OPTIONAL_DEF"; if (Inst.hasOptionalDef) OS << "|(1<<TID::HasOptionalDef)";
if (Inst.usesCustomDAGSchedInserter) if (Inst.usesCustomDAGSchedInserter)
OS << "|M_USES_CUSTOM_DAG_SCHED_INSERTION"; OS << "|(1<<TID::UsesCustomDAGSchedInserter)";
if (Inst.isVariadic) OS << "|M_VARIADIC"; if (Inst.isVariadic) OS << "|(1<<TID::Variadic)";
if (Inst.mayHaveSideEffects) OS << "|M_MAY_HAVE_SIDE_EFFECTS"; if (Inst.mayHaveSideEffects) OS << "|(1<<TID::MayHaveSideEffects)";
if (NeverHasSideEffects) OS << "|M_NEVER_HAS_SIDE_EFFECTS"; if (NeverHasSideEffects) OS << "|(1<<TID::NeverHasSideEffects)";
OS << ", 0"; OS << ", 0";
// Emit all of the target-specific flags... // Emit all of the target-specific flags...