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Add MIPS accumulator and DSP control registers.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164429 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Akira Hatanaka 2012-09-21 23:48:37 +00:00
parent a9adbf6df7
commit 1024f290d1
2 changed files with 45 additions and 1 deletions
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3
lib/Target/Mips/MipsRegisterInfo.cpp
View File

@ -123,6 +123,9 @@ getReservedRegs(const MachineFunction &MF) const {
Reserved.set(Mips::HWR29);
Reserved.set(Mips::HWR29_64);
// Reserve DSP control register.
Reserved.set(Mips::DSPCtrl);
// Reserve RA if in mips16 mode.
if (Subtarget.inMips16Mode()) {
Reserved.set(Mips::RA);

43
lib/Target/Mips/MipsRegisterInfo.td
View File

@ -245,13 +245,45 @@ let Namespace = "Mips" in {
// Hardware register $29
def HWR29 : Register<"29">;
def HWR29_64 : Register<"29">;
// Accum registers
def LO0 : Register<"ac0"> {
let Aliases = [LO];
}
def HI0 : Register<"hi0"> {
let Aliases = [HI];
}
def LO1 : Register<"ac1">;
def HI1 : Register<"hi1">;
def LO2 : Register<"ac2">;
def HI2 : Register<"hi2">;
def LO3 : Register<"ac3">;
def HI3 : Register<"hi3">;
let SubRegIndices = [sub_32] in {
def LO0_64 : RegisterWithSubRegs<"ac0", [LO0]> {
let Aliases = [LO64];
}
def HI0_64 : RegisterWithSubRegs<"hi0", [HI0]> {
let Aliases = [HI64];
}
def LO1_64 : RegisterWithSubRegs<"ac1", [LO1]>;
def HI1_64 : RegisterWithSubRegs<"hi1", [HI1]>;
def LO2_64 : RegisterWithSubRegs<"ac2", [LO2]>;
def HI2_64 : RegisterWithSubRegs<"hi2", [HI2]>;
def LO3_64 : RegisterWithSubRegs<"ac3", [LO3]>;
def HI3_64 : RegisterWithSubRegs<"hi3", [HI3]>;
}
def DSPCtrl : Register<"dspctrl">;
}
//===----------------------------------------------------------------------===//
// Register Classes
//===----------------------------------------------------------------------===//
def CPURegs : RegisterClass<"Mips", [i32], 32, (add
class CPURegsClass<list<ValueType> regTypes> :
RegisterClass<"Mips", regTypes, 32, (add
// Reserved
ZERO, AT,
// Return Values and Arguments
@ -265,6 +297,9 @@ def CPURegs : RegisterClass<"Mips", [i32], 32, (add
// Reserved
K0, K1, GP, SP, FP, RA)>;
def CPURegs : CPURegsClass<[i32]>;
def DSPRegs : CPURegsClass<[v4i8, v2i16]>;
def CPU64Regs : RegisterClass<"Mips", [i64], 64, (add
// Reserved
ZERO_64, AT_64,
@ -322,3 +357,9 @@ def HILO64 : RegisterClass<"Mips", [i64], 64, (add HI64, LO64)>;
def HWRegs : RegisterClass<"Mips", [i32], 32, (add HWR29)>;
def HWRegs64 : RegisterClass<"Mips", [i64], 32, (add HWR29_64)>;
// Accum Registers
def HIRegs : RegisterClass<"Mips", [i32], 32, (sequence "HI%u", 0, 3)>;
def LORegs : RegisterClass<"Mips", [i32], 32, (sequence "LO%u", 0, 3)>;
def HI64Regs : RegisterClass<"Mips", [i64], 64, (sequence "HI%u_64", 0, 3)>;
def LO64Regs : RegisterClass<"Mips", [i64], 64, (sequence "LO%u_64", 0, 3)>;