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Constraint register class with constrainRegClass() to CSE a virtual into another. rdar://10293289
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142234 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -1196,6 +1196,7 @@ bool MachineLICM::EliminateCSE(MachineInstr *MI,
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// Replace virtual registers defined by MI by their counterparts defined
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// Replace virtual registers defined by MI by their counterparts defined
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// by Dup.
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// by Dup.
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SmallVector<unsigned, 2> Defs;
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for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
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for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
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const MachineOperand &MO = MI->getOperand(i);
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const MachineOperand &MO = MI->getOperand(i);
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@ -1206,11 +1207,33 @@ bool MachineLICM::EliminateCSE(MachineInstr *MI,
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"Instructions with different phys regs are not identical!");
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"Instructions with different phys regs are not identical!");
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if (MO.isReg() && MO.isDef() &&
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if (MO.isReg() && MO.isDef() &&
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!TargetRegisterInfo::isPhysicalRegister(MO.getReg())) {
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!TargetRegisterInfo::isPhysicalRegister(MO.getReg()))
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MRI->replaceRegWith(MO.getReg(), Dup->getOperand(i).getReg());
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Defs.push_back(i);
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MRI->clearKillFlags(Dup->getOperand(i).getReg());
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}
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SmallVector<const TargetRegisterClass*, 2> OrigRCs;
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for (unsigned i = 0, e = Defs.size(); i != e; ++i) {
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unsigned Idx = Defs[i];
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unsigned Reg = MI->getOperand(Idx).getReg();
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unsigned DupReg = Dup->getOperand(Idx).getReg();
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OrigRCs.push_back(MRI->getRegClass(DupReg));
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if (!MRI->constrainRegClass(DupReg, MRI->getRegClass(Reg))) {
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// Restore old RCs if more than one defs.
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for (unsigned j = 0; j != i; ++j)
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MRI->setRegClass(Dup->getOperand(Defs[j]).getReg(), OrigRCs[j]);
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return false;
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}
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}
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}
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}
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for (unsigned i = 0, e = Defs.size(); i != e; ++i) {
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unsigned Idx = Defs[i];
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unsigned Reg = MI->getOperand(Idx).getReg();
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unsigned DupReg = Dup->getOperand(Idx).getReg();
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MRI->replaceRegWith(Reg, DupReg);
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MRI->clearKillFlags(DupReg);
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}
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MI->eraseFromParent();
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MI->eraseFromParent();
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++NumCSEed;
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++NumCSEed;
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return true;
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return true;
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