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Fix some trailing issues from my introduction of MVT::untyped and its use for REGISTER_SEQUENCE.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133567 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Owen Anderson 2011-06-21 22:54:23 +00:00
parent 94d4c91bc5
commit 109c22c062
2 changed files with 12 additions and 1 deletions
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12
lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
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@ -290,7 +290,17 @@ static void GetCostForDef(const ScheduleDAGSDNodes::RegDefIter &RegDefPos,
// Special handling for untyped values. These values can only come from // Special handling for untyped values. These values can only come from
// the expansion of custom DAG-to-DAG patterns. // the expansion of custom DAG-to-DAG patterns.
if (VT == MVT::untyped) { if (VT == MVT::untyped) {
unsigned Opcode = RegDefPos.GetNode()->getMachineOpcode(); const SDNode *Node = RegDefPos.GetNode();
unsigned Opcode = Node->getMachineOpcode();
if (Opcode == TargetOpcode::REG_SEQUENCE) {
unsigned DstRCIdx = cast<ConstantSDNode>(Node->getOperand(0))->getZExtValue();
const TargetRegisterClass *RC = TRI->getRegClass(DstRCIdx);
RegClass = RC->getID();
Cost = 1;
return;
}
unsigned Idx = RegDefPos.GetIdx(); unsigned Idx = RegDefPos.GetIdx();
const TargetInstrDesc Desc = TII->get(Opcode); const TargetInstrDesc Desc = TII->get(Opcode);
const TargetRegisterClass *RC = Desc.getRegClass(Idx, TRI); const TargetRegisterClass *RC = Desc.getRegClass(Idx, TRI);

1
lib/VMCore/ValueTypes.cpp
View File

@ -133,6 +133,7 @@ std::string EVT::getEVTString() const {
case MVT::v2f64: return "v2f64"; case MVT::v2f64: return "v2f64";
case MVT::v4f64: return "v4f64"; case MVT::v4f64: return "v4f64";
case MVT::Metadata:return "Metadata"; case MVT::Metadata:return "Metadata";
case MVT::untyped: return "untyped";
} }
} }