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Spill multiple registers at once.
Live range splitting can create a number of small live ranges containing only a single real use. Spill these small live ranges along with the large range they are connected to with copies. This enables memory operand folding and maximizes the spill to fill distance. Work in progress with known bugs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127529 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jakob Stoklund Olesen
parent
7a387e4d9d
commit
10a433238f
@ -48,6 +48,13 @@ class InlineSpiller : public Spiller {
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const TargetRegisterClass *rc_;
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int stackSlot_;
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// All registers to spill to stackSlot_, including the main register.
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SmallVector<unsigned, 8> RegsToSpill;
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// All COPY instructions to/from snippets.
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// They are ignored since both operands refer to the same stack slot.
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SmallPtrSet<MachineInstr*, 8> SnippetCopies;
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// Values that failed to remat at some point.
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SmallPtrSet<VNInfo*, 8> usedValues_;
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@ -72,15 +79,21 @@ public:
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void spill(LiveRangeEdit &);
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private:
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bool isSnippet(const LiveInterval &SnipLI);
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void collectRegsToSpill();
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bool reMaterializeFor(MachineBasicBlock::iterator MI);
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void reMaterializeAll();
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bool coalesceStackAccess(MachineInstr *MI);
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bool coalesceStackAccess(MachineInstr *MI, unsigned Reg);
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bool foldMemoryOperand(MachineBasicBlock::iterator MI,
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const SmallVectorImpl<unsigned> &Ops,
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MachineInstr *LoadMI = 0);
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void insertReload(LiveInterval &NewLI, MachineBasicBlock::iterator MI);
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void insertSpill(LiveInterval &NewLI, MachineBasicBlock::iterator MI);
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void insertSpill(LiveInterval &NewLI, const LiveInterval &OldLI,
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MachineBasicBlock::iterator MI);
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void spillAroundUses(unsigned Reg);
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};
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}
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@ -92,6 +105,114 @@ Spiller *createInlineSpiller(MachineFunctionPass &pass,
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}
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}
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//===----------------------------------------------------------------------===//
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// Snippets
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//===----------------------------------------------------------------------===//
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// When spilling a virtual register, we also spill any snippets it is connected
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// to. The snippets are small live ranges that only have a single real use,
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// leftovers from live range splitting. Spilling them enables memory operand
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// folding or tightens the live range around the single use.
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//
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// This minimizes register pressure and maximizes the store-to-load distance for
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// spill slots which can be important in tight loops.
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/// isFullCopyOf - If MI is a COPY to or from Reg, return the other register,
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/// otherwise return 0.
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static unsigned isFullCopyOf(const MachineInstr *MI, unsigned Reg) {
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if (!MI->isCopy())
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return 0;
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if (MI->getOperand(0).getSubReg() != 0)
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return 0;
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if (MI->getOperand(1).getSubReg() != 0)
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return 0;
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if (MI->getOperand(0).getReg() == Reg)
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return MI->getOperand(1).getReg();
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if (MI->getOperand(1).getReg() == Reg)
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return MI->getOperand(0).getReg();
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return 0;
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}
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/// isSnippet - Identify if a live interval is a snippet that should be spilled.
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/// It is assumed that SnipLI is a virtual register with the same original as
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/// edit_->getReg().
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bool InlineSpiller::isSnippet(const LiveInterval &SnipLI) {
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unsigned Reg = edit_->getReg();
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// A snippet is a tiny live range with only a single instruction using it
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// besides copies to/from Reg or spills/fills. We accept:
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//
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// %snip = COPY %Reg / FILL fi#
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// %snip = USE %snip
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// %Reg = COPY %snip / SPILL %snip, fi#
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//
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if (SnipLI.getNumValNums() > 2 || !lis_.intervalIsInOneMBB(SnipLI))
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return false;
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MachineInstr *UseMI = 0;
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// Check that all uses satisfy our criteria.
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for (MachineRegisterInfo::reg_nodbg_iterator
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RI = mri_.reg_nodbg_begin(SnipLI.reg);
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MachineInstr *MI = RI.skipInstruction();) {
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// Allow copies to/from Reg.
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if (isFullCopyOf(MI, Reg))
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continue;
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// Allow stack slot loads.
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int FI;
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if (SnipLI.reg == tii_.isLoadFromStackSlot(MI, FI) && FI == stackSlot_)
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continue;
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// Allow stack slot stores.
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if (SnipLI.reg == tii_.isStoreToStackSlot(MI, FI) && FI == stackSlot_)
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continue;
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// Allow a single additional instruction.
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if (UseMI && MI != UseMI)
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return false;
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UseMI = MI;
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}
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return true;
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}
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/// collectRegsToSpill - Collect live range snippets that only have a single
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/// real use.
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void InlineSpiller::collectRegsToSpill() {
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unsigned Reg = edit_->getReg();
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unsigned Orig = vrm_.getOriginal(Reg);
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// Main register always spills.
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RegsToSpill.assign(1, Reg);
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SnippetCopies.clear();
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// Snippets all have the same original, so there can't be any for an original
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// register.
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if (Orig == Reg)
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return;
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for (MachineRegisterInfo::reg_iterator RI = mri_.reg_begin(Reg);
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MachineInstr *MI = RI.skipInstruction();) {
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unsigned SnipReg = isFullCopyOf(MI, Reg);
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if (!SnipReg)
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continue;
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if (!TargetRegisterInfo::isVirtualRegister(SnipReg))
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continue;
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if (vrm_.getOriginal(SnipReg) != Orig)
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continue;
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LiveInterval &SnipLI = lis_.getInterval(SnipReg);
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if (!isSnippet(SnipLI))
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continue;
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SnippetCopies.insert(MI);
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if (std::find(RegsToSpill.begin(), RegsToSpill.end(),
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SnipReg) == RegsToSpill.end())
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RegsToSpill.push_back(SnipReg);
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DEBUG(dbgs() << "\talso spill snippet " << SnipLI << '\n');
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}
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}
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/// reMaterializeFor - Attempt to rematerialize before MI instead of reloading.
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bool InlineSpiller::reMaterializeFor(MachineBasicBlock::iterator MI) {
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SlotIndex UseIdx = lis_.getInstructionIndex(MI).getUseIndex();
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@ -108,6 +229,12 @@ bool InlineSpiller::reMaterializeFor(MachineBasicBlock::iterator MI) {
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return true;
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}
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// FIXME: Properly remat for snippets as well.
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if (SnippetCopies.count(MI)) {
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usedValues_.insert(OrigVNI);
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return false;
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}
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LiveRangeEdit::Remat RM(OrigVNI);
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if (!edit_->canRematerializeAt(RM, UseIdx, false, lis_)) {
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usedValues_.insert(OrigVNI);
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@ -228,15 +355,15 @@ void InlineSpiller::reMaterializeAll() {
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}
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/// If MI is a load or store of stackSlot_, it can be removed.
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bool InlineSpiller::coalesceStackAccess(MachineInstr *MI) {
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bool InlineSpiller::coalesceStackAccess(MachineInstr *MI, unsigned Reg) {
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int FI = 0;
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unsigned reg;
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if (!(reg = tii_.isLoadFromStackSlot(MI, FI)) &&
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!(reg = tii_.isStoreToStackSlot(MI, FI)))
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unsigned InstrReg;
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if (!(InstrReg = tii_.isLoadFromStackSlot(MI, FI)) &&
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!(InstrReg = tii_.isStoreToStackSlot(MI, FI)))
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return false;
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// We have a stack access. Is it the right register and slot?
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if (reg != edit_->getReg() || FI != stackSlot_)
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if (InstrReg != Reg || FI != stackSlot_)
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return false;
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DEBUG(dbgs() << "Coalescing stack access: " << *MI);
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@ -301,13 +428,13 @@ void InlineSpiller::insertReload(LiveInterval &NewLI,
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}
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/// insertSpill - Insert a spill of NewLI.reg after MI.
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void InlineSpiller::insertSpill(LiveInterval &NewLI,
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void InlineSpiller::insertSpill(LiveInterval &NewLI, const LiveInterval &OldLI,
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MachineBasicBlock::iterator MI) {
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MachineBasicBlock &MBB = *MI->getParent();
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// Get the defined value. It could be an early clobber so keep the def index.
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SlotIndex Idx = lis_.getInstructionIndex(MI).getDefIndex();
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VNInfo *VNI = edit_->getParent().getVNInfoAt(Idx);
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VNInfo *VNI = OldLI.getVNInfoAt(Idx);
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assert(VNI && VNI->def.getDefIndex() == Idx && "Inconsistent VNInfo");
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Idx = VNI->def;
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@ -320,42 +447,12 @@ void InlineSpiller::insertSpill(LiveInterval &NewLI,
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NewLI.addRange(LiveRange(Idx, StoreIdx, StoreVNI));
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}
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void InlineSpiller::spill(LiveRangeEdit &edit) {
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edit_ = &edit;
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assert(!TargetRegisterInfo::isStackSlot(edit.getReg())
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&& "Trying to spill a stack slot.");
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DEBUG(dbgs() << "Inline spilling "
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<< mri_.getRegClass(edit.getReg())->getName()
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<< ':' << edit.getParent() << "\nFrom original "
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<< PrintReg(vrm_.getOriginal(edit.getReg())) << '\n');
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assert(edit.getParent().isSpillable() &&
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"Attempting to spill already spilled value.");
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/// spillAroundUses - insert spill code around each use of Reg.
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void InlineSpiller::spillAroundUses(unsigned Reg) {
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LiveInterval &OldLI = lis_.getInterval(Reg);
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reMaterializeAll();
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// Remat may handle everything.
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if (edit_->getParent().empty())
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return;
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rc_ = mri_.getRegClass(edit.getReg());
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// Share a stack slot among all descendants of Orig.
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unsigned Orig = vrm_.getOriginal(edit.getReg());
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stackSlot_ = vrm_.getStackSlot(Orig);
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if (stackSlot_ == VirtRegMap::NO_STACK_SLOT)
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stackSlot_ = vrm_.assignVirt2StackSlot(Orig);
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if (Orig != edit.getReg())
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vrm_.assignVirt2StackSlot(edit.getReg(), stackSlot_);
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// Update LiveStacks now that we are committed to spilling.
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LiveInterval &stacklvr = lss_.getOrCreateInterval(stackSlot_, rc_);
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if (!stacklvr.hasAtLeastOneValue())
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stacklvr.getNextValue(SlotIndex(), 0, lss_.getVNInfoAllocator());
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stacklvr.MergeRangesInAsValue(edit_->getParent(), stacklvr.getValNumInfo(0));
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// Iterate over instructions using register.
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for (MachineRegisterInfo::reg_iterator RI = mri_.reg_begin(edit.getReg());
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// Iterate over instructions using Reg.
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for (MachineRegisterInfo::reg_iterator RI = mri_.reg_begin(Reg);
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MachineInstr *MI = RI.skipInstruction();) {
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// Debug values are not allowed to affect codegen.
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@ -376,14 +473,18 @@ void InlineSpiller::spill(LiveRangeEdit &edit) {
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continue;
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}
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// Ignore copies to/from snippets. We'll delete them.
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if (SnippetCopies.count(MI))
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continue;
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// Stack slot accesses may coalesce away.
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if (coalesceStackAccess(MI))
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if (coalesceStackAccess(MI, Reg))
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continue;
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// Analyze instruction.
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bool Reads, Writes;
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SmallVector<unsigned, 8> Ops;
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tie(Reads, Writes) = MI->readsWritesVirtualRegister(edit.getReg(), &Ops);
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tie(Reads, Writes) = MI->readsWritesVirtualRegister(Reg, &Ops);
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// Attempt to fold memory ops.
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if (foldMemoryOperand(MI, Ops))
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@ -391,7 +492,7 @@ void InlineSpiller::spill(LiveRangeEdit &edit) {
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// Allocate interval around instruction.
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// FIXME: Infer regclass from instruction alone.
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LiveInterval &NewLI = edit.create(mri_, lis_, vrm_);
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LiveInterval &NewLI = edit_->create(mri_, lis_, vrm_);
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NewLI.markNotSpillable();
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if (Reads)
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@ -413,8 +514,62 @@ void InlineSpiller::spill(LiveRangeEdit &edit) {
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// FIXME: Use a second vreg if instruction has no tied ops.
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if (Writes && hasLiveDef)
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insertSpill(NewLI, MI);
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insertSpill(NewLI, OldLI, MI);
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DEBUG(dbgs() << "\tinterval: " << NewLI << '\n');
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}
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}
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void InlineSpiller::spill(LiveRangeEdit &edit) {
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edit_ = &edit;
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assert(!TargetRegisterInfo::isStackSlot(edit.getReg())
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&& "Trying to spill a stack slot.");
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DEBUG(dbgs() << "Inline spilling "
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<< mri_.getRegClass(edit.getReg())->getName()
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<< ':' << edit.getParent() << "\nFrom original "
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<< PrintReg(vrm_.getOriginal(edit.getReg())) << '\n');
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assert(edit.getParent().isSpillable() &&
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"Attempting to spill already spilled value.");
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// Share a stack slot among all descendants of Orig.
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unsigned Orig = vrm_.getOriginal(edit.getReg());
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stackSlot_ = vrm_.getStackSlot(Orig);
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collectRegsToSpill();
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reMaterializeAll();
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// Remat may handle everything.
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if (edit_->getParent().empty())
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return;
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rc_ = mri_.getRegClass(edit.getReg());
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if (stackSlot_ == VirtRegMap::NO_STACK_SLOT)
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stackSlot_ = vrm_.assignVirt2StackSlot(Orig);
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if (Orig != edit.getReg())
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vrm_.assignVirt2StackSlot(edit.getReg(), stackSlot_);
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// Update LiveStacks now that we are committed to spilling.
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LiveInterval &stacklvr = lss_.getOrCreateInterval(stackSlot_, rc_);
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if (!stacklvr.hasAtLeastOneValue())
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stacklvr.getNextValue(SlotIndex(), 0, lss_.getVNInfoAllocator());
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stacklvr.MergeRangesInAsValue(edit_->getParent(), stacklvr.getValNumInfo(0));
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// Spill around uses of all RegsToSpill.
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for (unsigned i = 0, e = RegsToSpill.size(); i != e; ++i)
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spillAroundUses(RegsToSpill[i]);
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// Finally delete the SnippetCopies.
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for (MachineRegisterInfo::reg_iterator RI = mri_.reg_begin(edit.getReg());
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MachineInstr *MI = RI.skipInstruction();) {
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assert(SnippetCopies.count(MI) && "Remaining use wasn't a snippet copy");
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// FIXME: Do this with a LiveRangeEdit callback.
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vrm_.RemoveMachineInstrFromMaps(MI);
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lis_.RemoveMachineInstrFromMaps(MI);
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MI->eraseFromParent();
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}
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// FIXME: Notify the register allocator that the snippets are now dead.
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}
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@ -289,6 +289,13 @@ void RegAllocBase::allocatePhysRegs() {
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// Continue assigning vregs one at a time to available physical registers.
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while (LiveInterval *VirtReg = dequeue()) {
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// Unused registers can appear when the spiller coalesces snippets.
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if (MRI->reg_nodbg_empty(VirtReg->reg)) {
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DEBUG(dbgs() << "Dropping unused " << *VirtReg << '\n');
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LIS->removeInterval(VirtReg->reg);
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continue;
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}
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// selectOrSplit requests the allocator to return an available physical
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// register if possible and populate a list of new live intervals that
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// result from splitting.
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