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AVX-512: Scalar ERI intrinsics
including SAE mode and memory operand. Added AVX512_maskable_scalar template, that should cover all scalar instructions in the future. The main difference between AVX512_maskable_scalar<> and AVX512_maskable<> is using X86select instead of vselect. I need it, because I can't create vselect node for MVT::i1 mask for scalar instruction. http://reviews.llvm.org/D6378 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222820 91177308-0d34-0410-b5e6-96231b3b80d8
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@@ -16799,6 +16799,23 @@ static SDValue getVectorMaskingNode(SDValue Op, SDValue Mask,
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return DAG.getNode(ISD::VSELECT, dl, VT, VMask, Op, PreservedSrc);
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}
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static SDValue getScalarMaskingNode(SDValue Op, SDValue Mask,
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SDValue PreservedSrc,
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const X86Subtarget *Subtarget,
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SelectionDAG &DAG) {
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if (isAllOnes(Mask))
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return Op;
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EVT VT = Op.getValueType();
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SDLoc dl(Op);
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// The mask should be of type MVT::i1
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SDValue IMask = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, Mask);
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if (PreservedSrc.getOpcode() == ISD::UNDEF)
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PreservedSrc = getZeroVector(VT, Subtarget, DAG, dl);
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return DAG.getNode(X86ISD::SELECT, dl, VT, IMask, Op, PreservedSrc);
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}
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static unsigned getOpcodeForFMAIntrinsic(unsigned IntNo) {
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switch (IntNo) {
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default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
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@@ -16872,6 +16889,16 @@ static SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, const X86Subtarget *Subtarget
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RoundingMode),
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Mask, Src0, Subtarget, DAG);
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}
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case INTR_TYPE_SCALAR_MASK_RM: {
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SDValue Src1 = Op.getOperand(1);
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SDValue Src2 = Op.getOperand(2);
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SDValue Src0 = Op.getOperand(3);
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SDValue Mask = Op.getOperand(4);
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SDValue RoundingMode = Op.getOperand(5);
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return getScalarMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src1, Src2,
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RoundingMode),
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Mask, Src0, Subtarget, DAG);
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}
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case INTR_TYPE_2OP_MASK: {
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return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Op.getOperand(1),
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Op.getOperand(2)),
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