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[mips][mips64r6] Add R_MIPS_PC19_S2

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Differential Revision: http://reviews.llvm.org/D3866


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210773 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Zoran Jovanovic
2014-06-12 12:40:00 +00:00
parent 9ac3cc8a25
commit 10ce787fa5
7 changed files with 72 additions and 16 deletions
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20
lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp
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@@ -621,11 +621,21 @@ unsigned
MipsMCCodeEmitter::getSimm19Lsl2Encoding(const MCInst &MI, unsigned OpNo,
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const {
assert(MI.getOperand(OpNo).isImm());
// The immediate is encoded as 'immediate << 2'.
unsigned Res = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, STI);
assert((Res & 3) == 0);
return Res >> 2;
const MCOperand &MO = MI.getOperand(OpNo);
if (MO.isImm()) {
// The immediate is encoded as 'immediate << 2'.
unsigned Res = getMachineOpValue(MI, MO, Fixups, STI);
assert((Res & 3) == 0);
return Res >> 2;
}
assert(MO.isExpr() &&
"getSimm19Lsl2Encoding expects only expressions or an immediate");
const MCExpr *Expr = MO.getExpr();
Fixups.push_back(MCFixup::Create(0, Expr,
MCFixupKind(Mips::fixup_MIPS_PC19_S2)));
return 0;
}
unsigned