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[ARM64] Increases the Sched Model accuracy for Cortex-A53.
Patch by Dave Estes <cestes@codeaurora.org> http://reviews.llvm.org/D3769 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209001 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chad Rosier
parent
3258443195
commit
117b038592
@ -1101,7 +1101,7 @@ class BaseOneOperandData<bits<3> opc, RegisterClass regtype, string asm,
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SDPatternOperator node>
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: I<(outs regtype:$Rd), (ins regtype:$Rn), asm, "\t$Rd, $Rn", "",
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[(set regtype:$Rd, (node regtype:$Rn))]>,
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Sched<[WriteI]> {
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Sched<[WriteI, ReadI]> {
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bits<5> Rd;
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bits<5> Rn;
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@ -1140,7 +1140,7 @@ class BaseBaseAddSubCarry<bit isSub, RegisterClass regtype, string asm,
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list<dag> pattern>
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: I<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm),
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asm, "\t$Rd, $Rn, $Rm", "", pattern>,
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Sched<[WriteI]> {
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Sched<[WriteI, ReadI, ReadI]> {
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let Uses = [NZCV];
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bits<5> Rd;
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bits<5> Rn;
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@ -1214,11 +1214,11 @@ class BaseDiv<bit isSigned, RegisterClass regtype, string asm,
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multiclass Div<bit isSigned, string asm, SDPatternOperator OpNode> {
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def Wr : BaseDiv<isSigned, GPR32, asm, OpNode>,
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Sched<[WriteID32]> {
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Sched<[WriteID32, ReadID, ReadID]> {
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let Inst{31} = 0;
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}
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def Xr : BaseDiv<isSigned, GPR64, asm, OpNode>,
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Sched<[WriteID64]> {
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Sched<[WriteID64, ReadID, ReadID]> {
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let Inst{31} = 1;
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}
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}
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@ -1226,7 +1226,7 @@ multiclass Div<bit isSigned, string asm, SDPatternOperator OpNode> {
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class BaseShift<bits<2> shift_type, RegisterClass regtype, string asm,
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SDPatternOperator OpNode = null_frag>
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: BaseTwoOperand<{1,0,?,?}, regtype, asm, OpNode>,
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Sched<[WriteIS]> {
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Sched<[WriteIS, ReadI]> {
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let Inst{11-10} = shift_type;
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}
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@ -1278,13 +1278,13 @@ class BaseMulAccum<bit isSub, bits<3> opc, RegisterClass multype,
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multiclass MulAccum<bit isSub, string asm, SDNode AccNode> {
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def Wrrr : BaseMulAccum<isSub, 0b000, GPR32, GPR32, asm,
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[(set GPR32:$Rd, (AccNode GPR32:$Ra, (mul GPR32:$Rn, GPR32:$Rm)))]>,
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Sched<[WriteIM32]> {
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Sched<[WriteIM32, ReadIMA, ReadIM, ReadIM]> {
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let Inst{31} = 0;
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}
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def Xrrr : BaseMulAccum<isSub, 0b000, GPR64, GPR64, asm,
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[(set GPR64:$Rd, (AccNode GPR64:$Ra, (mul GPR64:$Rn, GPR64:$Rm)))]>,
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Sched<[WriteIM64]> {
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Sched<[WriteIM64, ReadIMA, ReadIM, ReadIM]> {
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let Inst{31} = 1;
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}
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}
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@ -1294,7 +1294,7 @@ class WideMulAccum<bit isSub, bits<3> opc, string asm,
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: BaseMulAccum<isSub, opc, GPR32, GPR64, asm,
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[(set GPR64:$Rd, (AccNode GPR64:$Ra,
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(mul (ExtNode GPR32:$Rn), (ExtNode GPR32:$Rm))))]>,
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Sched<[WriteIM32]> {
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Sched<[WriteIM32, ReadIMA, ReadIM, ReadIM]> {
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let Inst{31} = 1;
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}
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@ -1302,7 +1302,7 @@ class MulHi<bits<3> opc, string asm, SDNode OpNode>
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: I<(outs GPR64:$Rd), (ins GPR64:$Rn, GPR64:$Rm),
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asm, "\t$Rd, $Rn, $Rm", "",
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[(set GPR64:$Rd, (OpNode GPR64:$Rn, GPR64:$Rm))]>,
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Sched<[WriteIM64]> {
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Sched<[WriteIM64, ReadIM, ReadIM]> {
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bits<5> Rd;
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bits<5> Rn;
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bits<5> Rm;
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@ -1333,7 +1333,7 @@ class BaseCRC32<bit sf, bits<2> sz, bit C, RegisterClass StreamReg,
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: I<(outs GPR32:$Rd), (ins GPR32:$Rn, StreamReg:$Rm),
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asm, "\t$Rd, $Rn, $Rm", "",
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[(set GPR32:$Rd, (OpNode GPR32:$Rn, StreamReg:$Rm))]>,
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Sched<[WriteISReg]> {
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Sched<[WriteISReg, ReadI, ReadISReg]> {
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bits<5> Rd;
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bits<5> Rn;
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bits<5> Rm;
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@ -1420,7 +1420,7 @@ class BaseInsertImmediate<bits<2> opc, RegisterClass regtype, Operand shifter,
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: I<(outs regtype:$Rd),
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(ins regtype:$src, movimm32_imm:$imm, shifter:$shift),
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asm, "\t$Rd, $imm$shift", "$src = $Rd", []>,
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Sched<[WriteI]> {
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Sched<[WriteI, ReadI]> {
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bits<5> Rd;
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bits<16> imm;
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bits<6> shift;
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@ -1453,7 +1453,7 @@ class BaseAddSubImm<bit isSub, bit setFlags, RegisterClass dstRegtype,
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: I<(outs dstRegtype:$Rd), (ins srcRegtype:$Rn, immtype:$imm),
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asm, "\t$Rd, $Rn, $imm", "",
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[(set dstRegtype:$Rd, (OpNode srcRegtype:$Rn, immtype:$imm))]>,
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Sched<[WriteI]> {
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Sched<[WriteI, ReadI]> {
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bits<5> Rd;
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bits<5> Rn;
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bits<14> imm;
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@ -1471,7 +1471,7 @@ class BaseAddSubRegPseudo<RegisterClass regtype,
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SDPatternOperator OpNode>
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: Pseudo<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm),
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[(set regtype:$Rd, (OpNode regtype:$Rn, regtype:$Rm))]>,
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Sched<[WriteI]>;
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Sched<[WriteI, ReadI, ReadI]>;
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class BaseAddSubSReg<bit isSub, bit setFlags, RegisterClass regtype,
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arith_shifted_reg shifted_regtype, string asm,
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@ -1479,7 +1479,7 @@ class BaseAddSubSReg<bit isSub, bit setFlags, RegisterClass regtype,
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: I<(outs regtype:$Rd), (ins regtype:$Rn, shifted_regtype:$Rm),
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asm, "\t$Rd, $Rn, $Rm", "",
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[(set regtype:$Rd, (OpNode regtype:$Rn, shifted_regtype:$Rm))]>,
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Sched<[WriteISReg]> {
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Sched<[WriteISReg, ReadI, ReadISReg]> {
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// The operands are in order to match the 'addr' MI operands, so we
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// don't need an encoder method and by-name matching. Just use the default
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// in-order handling. Since we're using by-order, make sure the names
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@ -1508,7 +1508,7 @@ class BaseAddSubEReg<bit isSub, bit setFlags, RegisterClass dstRegtype,
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(ins src1Regtype:$R2, src2Regtype:$R3),
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asm, "\t$R1, $R2, $R3", "",
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[(set dstRegtype:$R1, (OpNode src1Regtype:$R2, src2Regtype:$R3))]>,
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Sched<[WriteIEReg]> {
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Sched<[WriteIEReg, ReadI, ReadIEReg]> {
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bits<5> Rd;
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bits<5> Rn;
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bits<5> Rm;
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@ -1533,7 +1533,7 @@ class BaseAddSubEReg64<bit isSub, bit setFlags, RegisterClass dstRegtype,
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: I<(outs dstRegtype:$Rd),
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(ins src1Regtype:$Rn, src2Regtype:$Rm, ext_op:$ext),
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asm, "\t$Rd, $Rn, $Rm$ext", "", []>,
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Sched<[WriteIEReg]> {
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Sched<[WriteIEReg, ReadI, ReadIEReg]> {
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bits<5> Rd;
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bits<5> Rn;
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bits<5> Rm;
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@ -1746,7 +1746,7 @@ class BaseBitfieldImm<bits<2> opc,
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RegisterClass regtype, Operand imm_type, string asm>
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: I<(outs regtype:$Rd), (ins regtype:$Rn, imm_type:$immr, imm_type:$imms),
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asm, "\t$Rd, $Rn, $immr, $imms", "", []>,
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Sched<[WriteIS]> {
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Sched<[WriteIS, ReadI]> {
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bits<5> Rd;
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bits<5> Rn;
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bits<6> immr;
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@ -1780,7 +1780,7 @@ class BaseBitfieldImmWith2RegArgs<bits<2> opc,
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: I<(outs regtype:$Rd), (ins regtype:$src, regtype:$Rn, imm_type:$immr,
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imm_type:$imms),
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asm, "\t$Rd, $Rn, $immr, $imms", "$src = $Rd", []>,
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Sched<[WriteIS]> {
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Sched<[WriteIS, ReadI]> {
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bits<5> Rd;
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bits<5> Rn;
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bits<6> immr;
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@ -1818,7 +1818,7 @@ class BaseLogicalImm<bits<2> opc, RegisterClass dregtype,
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list<dag> pattern>
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: I<(outs dregtype:$Rd), (ins sregtype:$Rn, imm_type:$imm),
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asm, "\t$Rd, $Rn, $imm", "", pattern>,
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Sched<[WriteI]> {
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Sched<[WriteI, ReadI]> {
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bits<5> Rd;
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bits<5> Rn;
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bits<13> imm;
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@ -1839,7 +1839,7 @@ class BaseLogicalSReg<bits<2> opc, bit N, RegisterClass regtype,
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list<dag> pattern>
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: I<(outs regtype:$Rd), (ins regtype:$Rn, shifted_regtype:$Rm),
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asm, "\t$Rd, $Rn, $Rm", "", pattern>,
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Sched<[WriteISReg]> {
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Sched<[WriteISReg, ReadI, ReadISReg]> {
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// The operands are in order to match the 'addr' MI operands, so we
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// don't need an encoder method and by-name matching. Just use the default
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// in-order handling. Since we're using by-order, make sure the names
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@ -1897,7 +1897,7 @@ multiclass LogicalImmS<bits<2> opc, string mnemonic, SDNode OpNode> {
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class BaseLogicalRegPseudo<RegisterClass regtype, SDPatternOperator OpNode>
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: Pseudo<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm),
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[(set regtype:$Rd, (OpNode regtype:$Rn, regtype:$Rm))]>,
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Sched<[WriteI]>;
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Sched<[WriteI, ReadI, ReadI]>;
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// Split from LogicalImm as not all instructions have both.
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multiclass LogicalReg<bits<2> opc, bit N, string mnemonic,
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@ -1953,7 +1953,7 @@ let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
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class BaseCondSetFlagsImm<bit op, RegisterClass regtype, string asm>
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: I<(outs), (ins regtype:$Rn, imm0_31:$imm, imm0_15:$nzcv, ccode:$cond),
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asm, "\t$Rn, $imm, $nzcv, $cond", "", []>,
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Sched<[WriteI]> {
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Sched<[WriteI, ReadI]> {
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let Uses = [NZCV];
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let Defs = [NZCV];
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@ -1985,7 +1985,7 @@ let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
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class BaseCondSetFlagsReg<bit op, RegisterClass regtype, string asm>
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: I<(outs), (ins regtype:$Rn, regtype:$Rm, imm0_15:$nzcv, ccode:$cond),
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asm, "\t$Rn, $Rm, $nzcv, $cond", "", []>,
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Sched<[WriteI]> {
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Sched<[WriteI, ReadI, ReadI]> {
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let Uses = [NZCV];
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let Defs = [NZCV];
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@ -2022,7 +2022,7 @@ class BaseCondSelect<bit op, bits<2> op2, RegisterClass regtype, string asm>
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asm, "\t$Rd, $Rn, $Rm, $cond", "",
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[(set regtype:$Rd,
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(ARM64csel regtype:$Rn, regtype:$Rm, (i32 imm:$cond), NZCV))]>,
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Sched<[WriteI]> {
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Sched<[WriteI, ReadI, ReadI]> {
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let Uses = [NZCV];
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bits<5> Rd;
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@ -2055,7 +2055,7 @@ class BaseCondSelectOp<bit op, bits<2> op2, RegisterClass regtype, string asm,
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[(set regtype:$Rd,
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(ARM64csel regtype:$Rn, (frag regtype:$Rm),
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(i32 imm:$cond), NZCV))]>,
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Sched<[WriteI]> {
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Sched<[WriteI, ReadI, ReadI]> {
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let Uses = [NZCV];
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bits<5> Rd;
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@ -825,6 +825,19 @@ bool ARM64InstrInfo::optimizeCompareInstr(
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return true;
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}
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/// Return true if this is this instruction has a non-zero immediate
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bool ARM64InstrInfo::hasNonZeroImm(const MachineInstr *MI) const {
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switch (MI->getOpcode()) {
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default:
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if (MI->getOperand(3).isImm()) {
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unsigned val = MI->getOperand(3).getImm();
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return (val != 0);
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}
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break;
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}
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return false;
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}
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// Return true if this instruction simply sets its single destination register
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// to zero. This is equivalent to a register rename of the zero-register.
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bool ARM64InstrInfo::isGPRZero(const MachineInstr *MI) const {
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@ -56,6 +56,9 @@ public:
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unsigned isStoreToStackSlot(const MachineInstr *MI,
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int &FrameIndex) const override;
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/// \brief Is there a non-zero immediate?
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bool hasNonZeroImm(const MachineInstr *MI) const;
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/// \brief Does this instruction set its full destination register to zero?
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bool isGPRZero(const MachineInstr *MI) const;
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@ -20,7 +20,7 @@ def CortexA53Model : SchedMachineModel {
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let MicroOpBufferSize = 0; // Explicitly set to zero since A53 is in-order.
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let IssueWidth = 2; // 2 micro-ops are dispatched per cycle.
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let MinLatency = 1 ; // OperandCycles are interpreted as MinLatency.
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let LoadLatency = 2; // Optimistic load latency assuming bypass.
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let LoadLatency = 3; // Optimistic load latency assuming bypass.
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// This is overriden by OperandCycles if the
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// Itineraries are queried instead.
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let MispredictPenalty = 9; // Based on "Cortex-A53 Software Optimisation
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@ -32,7 +32,7 @@ def CortexA53Model : SchedMachineModel {
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//===----------------------------------------------------------------------===//
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// Define each kind of processor resource and number available.
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// Modeling each pipeline as a ProcResource using the BufferSize = 0 since
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// Modeling each pipeline as a ProcResource using the BufferSize = 0 since
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// Cortex-A53 is in-order.
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def A53UnitALU : ProcResource<2> { let BufferSize = 0; } // Int ALU
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@ -50,16 +50,16 @@ def A53UnitFPMDS : ProcResource<1> { let BufferSize = 0; } // FP Mult/Div/Sqrt
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let SchedModel = CortexA53Model in {
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// ALU - These are reduced to 1 despite a true latency of 4 in order to easily
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// model forwarding logic. Once forwarding is properly modelled, then
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// they'll be corrected.
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def : WriteRes<WriteImm, [A53UnitALU]> { let Latency = 1; }
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def : WriteRes<WriteI, [A53UnitALU]> { let Latency = 1; }
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def : WriteRes<WriteISReg, [A53UnitALU]> { let Latency = 1; }
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def : WriteRes<WriteIEReg, [A53UnitALU]> { let Latency = 1; }
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def : WriteRes<WriteExtr, [A53UnitALU]> { let Latency = 1; }
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def : WriteRes<WriteIS, [A53UnitALU]> { let Latency = 1; }
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def : WriteRes<WriteAdr, [A53UnitALU]> { let Latency = 1; }
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// ALU - Despite having a full latency of 4, most of the ALU instructions can
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// forward a cycle earlier and then two cycles earlier in the case of a
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// shift-only instruction. These latencies will be incorrect when the
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// result cannot be forwarded, but modeling isn't rocket surgery.
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def : WriteRes<WriteImm, [A53UnitALU]> { let Latency = 3; }
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def : WriteRes<WriteI, [A53UnitALU]> { let Latency = 3; }
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def : WriteRes<WriteISReg, [A53UnitALU]> { let Latency = 3; }
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def : WriteRes<WriteIEReg, [A53UnitALU]> { let Latency = 3; }
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def : WriteRes<WriteIS, [A53UnitALU]> { let Latency = 2; }
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def : WriteRes<WriteExtr, [A53UnitALU]> { let Latency = 3; }
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// MAC
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def : WriteRes<WriteIM32, [A53UnitMAC]> { let Latency = 4; }
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@ -73,14 +73,41 @@ def : WriteRes<WriteID64, [A53UnitDiv]> { let Latency = 4; }
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def : WriteRes<WriteLD, [A53UnitLdSt]> { let Latency = 4; }
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def : WriteRes<WriteLDIdx, [A53UnitLdSt]> { let Latency = 4; }
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def : WriteRes<WriteLDHi, [A53UnitLdSt]> { let Latency = 4; }
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def : WriteRes<WriteVLD, [A53UnitLdSt]> { let Latency = 4; }
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// Vector Load - Vector loads take 1-5 cycles to issue. For the WriteVecLd
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// below, choosing the median of 3 which makes the latency 6.
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// May model this more carefully in the future. The remaining
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// A53WriteVLD# types represent the 1-5 cycle issues explicitly.
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def : WriteRes<WriteVLD, [A53UnitLdSt]> { let Latency = 6;
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let ResourceCycles = [3]; }
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def A53WriteVLD1 : SchedWriteRes<[A53UnitLdSt]> { let Latency = 4; }
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def A53WriteVLD2 : SchedWriteRes<[A53UnitLdSt]> { let Latency = 5;
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let ResourceCycles = [2]; }
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def A53WriteVLD3 : SchedWriteRes<[A53UnitLdSt]> { let Latency = 6;
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let ResourceCycles = [3]; }
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def A53WriteVLD4 : SchedWriteRes<[A53UnitLdSt]> { let Latency = 7;
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let ResourceCycles = [4]; }
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def A53WriteVLD5 : SchedWriteRes<[A53UnitLdSt]> { let Latency = 8;
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let ResourceCycles = [5]; }
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// Pre/Post Indexing - Performed as part of address generation which is already
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// accounted for in the WriteST* latencies below
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def : WriteRes<WriteAdr, []> { let Latency = 0; }
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// Store
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def : WriteRes<WriteST, [A53UnitLdSt]> { let Latency = 4; }
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def : WriteRes<WriteSTP, [A53UnitLdSt]> { let Latency = 4; }
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def : WriteRes<WriteSTIdx, [A53UnitLdSt]> { let Latency = 4; }
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def : WriteRes<WriteSTX, [A53UnitLdSt]> { let Latency = 4; }
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def : WriteRes<WriteVST, [A53UnitLdSt]> { let Latency = 4; }
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// Vector Store - Similar to vector loads, can take 1-3 cycles to issue.
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def : WriteRes<WriteVST, [A53UnitLdSt]> { let Latency = 5;
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let ResourceCycles = [2];}
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def A53WriteVST1 : SchedWriteRes<[A53UnitLdSt]> { let Latency = 4; }
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def A53WriteVST2 : SchedWriteRes<[A53UnitLdSt]> { let Latency = 5;
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let ResourceCycles = [2]; }
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def A53WriteVST3 : SchedWriteRes<[A53UnitLdSt]> { let Latency = 6;
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let ResourceCycles = [3]; }
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// Branch
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def : WriteRes<WriteBr, [A53UnitB]>;
|
||||
@ -101,29 +128,143 @@ def : WriteRes<WriteV, [A53UnitFPALU]> { let Latency = 6; }
|
||||
def : WriteRes<WriteFMul, [A53UnitFPMDS]> { let Latency = 6; }
|
||||
def : WriteRes<WriteFDiv, [A53UnitFPMDS]> { let Latency = 33;
|
||||
let ResourceCycles = [29]; }
|
||||
def A53WriteFDiv : SchedWriteRes<[A53UnitFPMDS]> { let Latency = 33;
|
||||
let ResourceCycles = [29]; }
|
||||
def A53WriteFSqrt : SchedWriteRes<[A53UnitFPMDS]> { let Latency = 32;
|
||||
let ResourceCycles = [28]; }
|
||||
def A53WriteFMAC : SchedWriteRes<[A53UnitFPMDS]> { let Latency = 10; }
|
||||
def A53WriteFDivSP : SchedWriteRes<[A53UnitFPMDS]> { let Latency = 18;
|
||||
let ResourceCycles = [14]; }
|
||||
def A53WriteFDivDP : SchedWriteRes<[A53UnitFPMDS]> { let Latency = 33;
|
||||
let ResourceCycles = [29]; }
|
||||
def A53WriteFSqrtSP : SchedWriteRes<[A53UnitFPMDS]> { let Latency = 17;
|
||||
let ResourceCycles = [13]; }
|
||||
def A53WriteFSqrtDP : SchedWriteRes<[A53UnitFPMDS]> { let Latency = 32;
|
||||
let ResourceCycles = [28]; }
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Subtarget-specific SchedRead types.
|
||||
|
||||
// While there is no forwarding information defined for these SchedRead types,
|
||||
// they are still used by some instruction via a SchedRW list and so these zero
|
||||
// SchedReadAdvances are required.
|
||||
|
||||
// No forwarding for these reads.
|
||||
def : ReadAdvance<ReadExtrHi, 0>;
|
||||
def : ReadAdvance<ReadAdrBase, 0>;
|
||||
def : ReadAdvance<ReadVLD, 0>;
|
||||
|
||||
// ALU - Most operands in the ALU pipes are not needed for two cycles. Shiftable
|
||||
// operands are needed one cycle later if and only if they are to be
|
||||
// shifted. Otherwise, they too are needed two cycle later.
|
||||
def : ReadAdvance<ReadI, 2, [WriteImm,WriteI,
|
||||
WriteISReg, WriteIEReg,WriteIS,
|
||||
WriteID32,WriteID64,
|
||||
WriteIM32,WriteIM64]>;
|
||||
def A53ReadShifted : SchedReadAdvance<1, [WriteImm,WriteI,
|
||||
WriteISReg, WriteIEReg,WriteIS,
|
||||
WriteID32,WriteID64,
|
||||
WriteIM32,WriteIM64]>;
|
||||
def A53ReadNotShifted : SchedReadAdvance<2, [WriteImm,WriteI,
|
||||
WriteISReg, WriteIEReg,WriteIS,
|
||||
WriteID32,WriteID64,
|
||||
WriteIM32,WriteIM64]>;
|
||||
def A53ReadISReg : SchedReadVariant<[
|
||||
SchedVar<RegShiftedPred, [A53ReadShifted]>,
|
||||
SchedVar<NoSchedPred, [A53ReadNotShifted]>]>;
|
||||
def : SchedAlias<ReadISReg, A53ReadISReg>;
|
||||
|
||||
def A53ReadIEReg : SchedReadVariant<[
|
||||
SchedVar<RegShiftedPred, [A53ReadShifted]>,
|
||||
SchedVar<NoSchedPred, [A53ReadNotShifted]>]>;
|
||||
def : SchedAlias<ReadIEReg, A53ReadIEReg>;
|
||||
|
||||
// MAC - Operands are generally needed one cycle later in the MAC pipe.
|
||||
// Accumulator operands are needed two cycles later.
|
||||
def : ReadAdvance<ReadIM, 1, [WriteImm,WriteI,
|
||||
WriteISReg, WriteIEReg,WriteIS,
|
||||
WriteID32,WriteID64,
|
||||
WriteIM32,WriteIM64]>;
|
||||
def : ReadAdvance<ReadIMA, 2, [WriteImm,WriteI,
|
||||
WriteISReg, WriteIEReg,WriteIS,
|
||||
WriteID32,WriteID64,
|
||||
WriteIM32,WriteIM64]>;
|
||||
|
||||
// Div
|
||||
def : ReadAdvance<ReadID, 1, [WriteImm,WriteI,
|
||||
WriteISReg, WriteIEReg,WriteIS,
|
||||
WriteID32,WriteID64,
|
||||
WriteIM32,WriteIM64]>;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Subtarget-specific InstRWs.
|
||||
|
||||
//---
|
||||
// Miscellaneous
|
||||
//---
|
||||
def : InstRW<[WriteI], (instrs COPY)>;
|
||||
def : InstRW<[WriteLD], (instregex "LD[1-4]")>;
|
||||
def : InstRW<[WriteST], (instregex "ST[1-4]")>;
|
||||
def : InstRW<[A53WriteFDiv], (instregex "^FDIV")>;
|
||||
def : InstRW<[A53WriteFSqrt], (instregex ".*SQRT.*")>;
|
||||
|
||||
//---
|
||||
// Vector Mul with Accumulate
|
||||
//---
|
||||
//def : InstRW<[WriteIM32, A53ReadIMA], (instregex "^M(ADD|SUB)W.*")>;
|
||||
//def : InstRW<[WriteIM64, A53ReadIMA], (instregex "^M(ADD|SUB)X.*")>;
|
||||
|
||||
//---
|
||||
// Vector Loads
|
||||
//---
|
||||
def : InstRW<[A53WriteVLD1], (instregex "LD1i(8|16|32|64)(_POST)?$")>;
|
||||
def : InstRW<[A53WriteVLD1], (instregex "LD1Rv(8b|4h|2s|1d|16b|8h|4s|2d)(_POST)?$")>;
|
||||
def : InstRW<[A53WriteVLD1], (instregex "LD1Onev(8b|4h|2s|1d|16b|8h|4s|2d)(_POST)?$")>;
|
||||
def : InstRW<[A53WriteVLD2], (instregex "LD1Twov(8b|4h|2s|1d|16b|8h|4s|2d)(_POST)?$")>;
|
||||
def : InstRW<[A53WriteVLD3], (instregex "LD1Threev(8b|4h|2s|1d|16b|8h|4s|2d)(_POST)?$")>;
|
||||
def : InstRW<[A53WriteVLD4], (instregex "LD1Fourv(8b|4h|2s|1d|16b|8h|4s|2d)(_POST)?$")>;
|
||||
|
||||
def : InstRW<[A53WriteVLD1], (instregex "LD2i(8|16|32|64)(_POST)?$")>;
|
||||
def : InstRW<[A53WriteVLD1], (instregex "LD2Rv(8b|4h|2s|1d|16b|8h|4s|2d)(_POST)?$")>;
|
||||
def : InstRW<[A53WriteVLD2], (instregex "LD2Twov(8b|4h|2s)(_POST)?$")>;
|
||||
def : InstRW<[A53WriteVLD4], (instregex "LD2Twov(16b|8h|4s|2d)(_POST)?$")>;
|
||||
|
||||
def : InstRW<[A53WriteVLD2], (instregex "LD3i(8|16|32|64)(_POST)?$")>;
|
||||
def : InstRW<[A53WriteVLD2], (instregex "LD3Rv(8b|4h|2s|1d|16b|8h|4s|2dq)(_POST)?$")>;
|
||||
def : InstRW<[A53WriteVLD4], (instregex "LD3Threev(8b|4h|2s|1d|16b|8h|4s)(_POST)?$")>;
|
||||
def : InstRW<[A53WriteVLD3], (instregex "LD3Threev(2d)(_POST)?$")>;
|
||||
|
||||
def : InstRW<[A53WriteVLD2], (instregex "LD4i(8|16|32|64)(_POST)?$")>;
|
||||
def : InstRW<[A53WriteVLD2], (instregex "LD4Rv(8b|4h|2s|1d|16b|8h|4s|2d)(_POST)?$")>;
|
||||
def : InstRW<[A53WriteVLD5], (instregex "LD4Fourv(8b|4h|2s|1d|16b|8h|4s)(_POST)?$")>;
|
||||
def : InstRW<[A53WriteVLD4], (instregex "LD4Fourv(2d)(_POST)?$")>;
|
||||
|
||||
def : InstRW<[A53WriteVLD1, A53WriteVLD1], (instregex "LDN?PS.*$")>;
|
||||
def : InstRW<[A53WriteVLD2, A53WriteVLD2], (instregex "LDN?PD.*$")>;
|
||||
def : InstRW<[A53WriteVLD4, A53WriteVLD4], (instregex "LDN?PQ.*$")>;
|
||||
|
||||
//---
|
||||
// Vector Stores
|
||||
//---
|
||||
def : InstRW<[A53WriteVST1], (instregex "ST1i(8|16|32|64)(_POST)?$")>;
|
||||
def : InstRW<[A53WriteVST1], (instregex "ST1Onev(8b|4h|2s|1d|16b|8h|4s|2d)(_POST)?$")>;
|
||||
def : InstRW<[A53WriteVST1], (instregex "ST1Twov(8b|4h|2s|1d|16b|8h|4s|2d)(_POST)?$")>;
|
||||
def : InstRW<[A53WriteVST2], (instregex "ST1Threev(8b|4h|2s|1d|16b|8h|4s|2d)(_POST)?$")>;
|
||||
def : InstRW<[A53WriteVST2], (instregex "ST1Fourv(8b|4h|2s|1d|16b|8h|4s|2d)(_POST)?$")>;
|
||||
|
||||
def : InstRW<[A53WriteVST1], (instregex "ST2i(8|16|32|64)(_POST)?$")>;
|
||||
def : InstRW<[A53WriteVST1], (instregex "ST2Twov(8b|4h|2s)(_POST)?$")>;
|
||||
def : InstRW<[A53WriteVST2], (instregex "ST2Twov(16b|8h|4s|2d)(_POST)?$")>;
|
||||
|
||||
def : InstRW<[A53WriteVST2], (instregex "ST3i(8|16|32|64)(_POST)?$")>;
|
||||
def : InstRW<[A53WriteVST3], (instregex "ST3Threev(8b|4h|2s|1d|16b|8h|4s)(_POST)?$")>;
|
||||
def : InstRW<[A53WriteVST2], (instregex "ST3Threev(2d)(_POST)?$")>;
|
||||
|
||||
def : InstRW<[A53WriteVST2], (instregex "ST4i(8|16|32|64)(_POST)?$")>;
|
||||
def : InstRW<[A53WriteVST3], (instregex "ST4Fourv(8b|4h|2s|1d|16b|8h|4s)(_POST)?$")>;
|
||||
def : InstRW<[A53WriteVST2], (instregex "ST4Fourv(2d)(_POST)?$")>;
|
||||
|
||||
def : InstRW<[A53WriteVST1], (instregex "STN?P(S|D).*$")>;
|
||||
def : InstRW<[A53WriteVST2], (instregex "STN?PQ.*$")>;
|
||||
|
||||
//---
|
||||
// Floating Point MAC, DIV, SQRT
|
||||
//---
|
||||
def : InstRW<[A53WriteFMAC], (instregex "^FN?M(ADD|SUB).*")>;
|
||||
def : InstRW<[A53WriteFMAC], (instregex "^FML(A|S).*")>;
|
||||
def : InstRW<[A53WriteFDivSP], (instrs FDIVSrr)>;
|
||||
def : InstRW<[A53WriteFDivDP], (instrs FDIVDrr)>;
|
||||
def : InstRW<[A53WriteFDivSP], (instregex "^FDIVv.*32$")>;
|
||||
def : InstRW<[A53WriteFDivDP], (instregex "^FDIVv.*64$")>;
|
||||
def : InstRW<[A53WriteFSqrtSP], (instregex "^.*SQRT.*32$")>;
|
||||
def : InstRW<[A53WriteFSqrtDP], (instregex "^.*SQRT.*64$")>;
|
||||
|
||||
}
|
||||
|
||||
@ -851,4 +851,15 @@ def : InstRW<[WriteAdr, WriteVSTPairShuffle], (instregex "ST4i(8|16|32)_POST")>;
|
||||
def : InstRW<[WriteVSTShuffle, WriteVSTShuffle], (instrs ST4i64)>;
|
||||
def : InstRW<[WriteAdr, WriteVSTShuffle, WriteVSTShuffle],(instrs ST4i64_POST)>;
|
||||
|
||||
//---
|
||||
// Unused SchedRead types
|
||||
//---
|
||||
|
||||
def : ReadAdvance<ReadI, 0>;
|
||||
def : ReadAdvance<ReadISReg, 0>;
|
||||
def : ReadAdvance<ReadIEReg, 0>;
|
||||
def : ReadAdvance<ReadIM, 0>;
|
||||
def : ReadAdvance<ReadIMA, 0>;
|
||||
def : ReadAdvance<ReadID, 0>;
|
||||
|
||||
} // SchedModel = CycloneModel
|
||||
|
||||
@ -25,13 +25,19 @@ def WriteImm : SchedWrite; // MOVN, MOVZ
|
||||
def WriteI : SchedWrite; // ALU
|
||||
def WriteISReg : SchedWrite; // ALU of Shifted-Reg
|
||||
def WriteIEReg : SchedWrite; // ALU of Extended-Reg
|
||||
def ReadI : SchedRead; // ALU
|
||||
def ReadISReg : SchedRead; // ALU of Shifted-Reg
|
||||
def ReadIEReg : SchedRead; // ALU of Extended-Reg
|
||||
def WriteExtr : SchedWrite; // EXTR shifts a reg pair
|
||||
def ReadExtrHi : SchedRead; // Read the high reg of the EXTR pair
|
||||
def WriteIS : SchedWrite; // Shift/Scale
|
||||
def WriteID32 : SchedWrite; // 32-bit Divide
|
||||
def WriteID64 : SchedWrite; // 64-bit Divide
|
||||
def ReadID : SchedRead; // 32/64-bit Divide
|
||||
def WriteIM32 : SchedWrite; // 32-bit Multiply
|
||||
def WriteIM64 : SchedWrite; // 64-bit Multiply
|
||||
def ReadIM : SchedRead; // 32/64-bit Multiply
|
||||
def ReadIMA : SchedRead; // 32/64-bit Multiply Accumulate
|
||||
def WriteBr : SchedWrite; // Branch
|
||||
def WriteBrReg : SchedWrite; // Indirect Branch
|
||||
|
||||
@ -44,6 +50,9 @@ def WriteLDIdx : SchedWrite; // Load from a register index (maybe scaled).
|
||||
def WriteSTIdx : SchedWrite; // Store to a register index (maybe scaled).
|
||||
def ReadAdrBase : SchedRead; // Read the base resister of a reg-offset LD/ST.
|
||||
|
||||
// Predicate for determining when a shiftable register is shifted.
|
||||
def RegShiftedPred : SchedPredicate<[{TII->hasNonZeroImm(MI)}]>;
|
||||
|
||||
// ScaledIdxPred is true if a WriteLDIdx operand will be
|
||||
// scaled. Subtargets can use this to dynamically select resources and
|
||||
// latency for WriteLDIdx and ReadAdrBase.
|
||||
|
||||
@ -8,9 +8,7 @@
|
||||
; CHECK: ********** MI Scheduling **********
|
||||
; CHECK: main
|
||||
; CHECK: *** Final schedule for BB#2 ***
|
||||
; CHECK: SU(13)
|
||||
; CHECK: MADDWrrr
|
||||
; CHECK: SU(4)
|
||||
; CHECK: ADDWri
|
||||
; CHECK: ********** INTERVALS **********
|
||||
@main.x = private unnamed_addr constant [8 x i32] [i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1], align 4
|
||||
|
||||
21
test/CodeGen/ARM64/misched-forwarding-A53.ll
Normal file
21
test/CodeGen/ARM64/misched-forwarding-A53.ll
Normal file
@ -0,0 +1,21 @@
|
||||
; REQUIRES: asserts
|
||||
; RUN: llc < %s -mtriple=arm64-linux-gnu -mcpu=cortex-a53 -pre-RA-sched=source -enable-misched -verify-misched -debug-only=misched -o - 2>&1 > /dev/null | FileCheck %s
|
||||
;
|
||||
; For Cortex-A53, shiftable operands that are not actually shifted
|
||||
; are not needed for an additional two cycles.
|
||||
;
|
||||
; CHECK: ********** MI Scheduling **********
|
||||
; CHECK: shiftable
|
||||
; CHECK: *** Final schedule for BB#0 ***
|
||||
; CHECK: ADDXrr %vreg0, %vreg2
|
||||
; CHECK: ADDXrs %vreg0, %vreg2, 5
|
||||
; CHECK: ********** INTERVALS **********
|
||||
define i64 @shiftable(i64 %A, i64 %B) {
|
||||
%tmp0 = sub i64 %B, 20
|
||||
%tmp1 = shl i64 %tmp0, 5;
|
||||
%tmp2 = add i64 %A, %tmp1;
|
||||
%tmp3 = add i64 %A, %tmp0
|
||||
%tmp4 = mul i64 %tmp2, %tmp3
|
||||
|
||||
ret i64 %tmp4
|
||||
}
|
||||
Loading…
x
Reference in New Issue
Block a user