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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42002 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Dale Johannesen 2007-09-16 16:51:49 +00:00
parent 656ab16c56
commit 118cd9dbba
1 changed files with 7 additions and 16 deletions
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23
lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
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@ -486,12 +486,7 @@ static SDOperand ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP,
// double.
MVT::ValueType VT = CFP->getValueType(0);
bool isDouble = VT == MVT::f64;
ConstantFP *LLVMC = ConstantFP::get(VT==MVT::f64 ? Type::DoubleTy :
VT==MVT::f32 ? Type::FloatTy :
VT==MVT::f80 ? Type::X86_FP80Ty :
VT==MVT::f128 ? Type::FP128Ty :
VT==MVT::ppcf128 ? Type::PPC_FP128Ty :
Type::VoidTy, // error
ConstantFP *LLVMC = ConstantFP::get(MVT::getTypeForValueType(VT),
CFP->getValueAPF());
if (!UseCP) {
if (VT!=MVT::f64 && VT!=MVT::f32)
@ -4620,12 +4615,9 @@ ExpandIntToFP(bool isSigned, MVT::ValueType DestTy, SDOperand Source) {
SDOperand FudgeInReg;
if (DestTy == MVT::f32)
FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx, NULL, 0);
else if (DestTy == MVT::f64)
else if (MVT::getSizeInBits(DestTy) > MVT::getSizeInBits(MVT::f32))
// FIXME: Avoid the extend by construction the right constantpool?
FudgeInReg = DAG.getExtLoad(ISD::EXTLOAD, MVT::f64, DAG.getEntryNode(),
CPIdx, NULL, 0, MVT::f32);
else if (DestTy == MVT::f80)
FudgeInReg = DAG.getExtLoad(ISD::EXTLOAD, MVT::f80, DAG.getEntryNode(),
FudgeInReg = DAG.getExtLoad(ISD::EXTLOAD, DestTy, DAG.getEntryNode(),
CPIdx, NULL, 0, MVT::f32);
else
assert(0 && "Unexpected conversion");
@ -4737,11 +4729,10 @@ SDOperand SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned,
if (DestVT == MVT::f64) {
// do nothing
Result = Sub;
} else if (DestVT == MVT::f32) {
// if f32 then cast to f32
Result = DAG.getNode(ISD::FP_ROUND, MVT::f32, Sub);
} else if (DestVT == MVT::f80) {
Result = DAG.getNode(ISD::FP_EXTEND, MVT::f80, Sub);
} else if (MVT::getSizeInBits(DestVT) < MVT::getSizeInBits(MVT::f64)) {
Result = DAG.getNode(ISD::FP_ROUND, DestVT, Sub);
} else if (MVT::getSizeInBits(DestVT) > MVT::getSizeInBits(MVT::f64)) {
Result = DAG.getNode(ISD::FP_EXTEND, DestVT, Sub);
}
return Result;
}