mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-11-02 07:11:49 +00:00
[PowerPC] Call support for fast-isel.
This patch adds fast-isel support for calls (but not intrinsic calls or varargs calls). It also removes a badly-formed assert. There are some new tests just for calls, and also for folding loads into arguments on calls to avoid extra extends. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189701 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bill Schmidt
parent
06f9db01ba
commit
11addd2a2f
@ -42,6 +42,17 @@ def RetCC_PPC : CallingConv<[
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// logic. FIXME: See if the logic can be simplified with use of CCs.
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// This may require some extensions to current table generation.
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// Simple calling convention for 64-bit ELF PowerPC fast isel.
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// Only handle ints and floats. All ints are promoted to i64.
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// Vector types and quadword ints are not handled.
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def CC_PPC64_ELF_FIS : CallingConv<[
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CCIfType<[i8], CCPromoteToType<i64>>,
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CCIfType<[i16], CCPromoteToType<i64>>,
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CCIfType<[i32], CCPromoteToType<i64>>,
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CCIfType<[i64], CCAssignToReg<[X3, X4, X5, X6, X7, X8, X9, X10]>>,
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CCIfType<[f32, f64], CCAssignToReg<[F1, F2, F3, F4, F5, F6, F7, F8]>>
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]>;
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// Simple return-value convention for 64-bit ELF PowerPC fast isel.
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// All small ints are promoted to i64. Vector types, quadword ints,
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// and multiple register returns are "supported" to avoid compile
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@ -114,6 +114,7 @@ class PPCFastISel : public FastISel {
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bool SelectIToFP(const Instruction *I, bool IsSigned);
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bool SelectFPToI(const Instruction *I, bool IsSigned);
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bool SelectBinaryIntOp(const Instruction *I, unsigned ISDOpcode);
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bool SelectCall(const Instruction *I);
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bool SelectRet(const Instruction *I);
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bool SelectIntExt(const Instruction *I);
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@ -145,6 +146,17 @@ class PPCFastISel : public FastISel {
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// Call handling routines.
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private:
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bool processCallArgs(SmallVectorImpl<Value*> &Args,
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SmallVectorImpl<unsigned> &ArgRegs,
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SmallVectorImpl<MVT> &ArgVTs,
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SmallVectorImpl<ISD::ArgFlagsTy> &ArgFlags,
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SmallVectorImpl<unsigned> &RegArgs,
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CallingConv::ID CC,
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unsigned &NumBytes,
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bool IsVarArg);
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void finishCall(MVT RetVT, SmallVectorImpl<unsigned> &UsedRegs,
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const Instruction *I, CallingConv::ID CC,
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unsigned &NumBytes, bool IsVarArg);
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CCAssignFn *usePPC32CCs(unsigned Flag);
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private:
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@ -1150,6 +1162,316 @@ bool PPCFastISel::SelectBinaryIntOp(const Instruction *I, unsigned ISDOpcode) {
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return true;
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}
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// Handle arguments to a call that we're attempting to fast-select.
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// Return false if the arguments are too complex for us at the moment.
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bool PPCFastISel::processCallArgs(SmallVectorImpl<Value*> &Args,
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SmallVectorImpl<unsigned> &ArgRegs,
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SmallVectorImpl<MVT> &ArgVTs,
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SmallVectorImpl<ISD::ArgFlagsTy> &ArgFlags,
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SmallVectorImpl<unsigned> &RegArgs,
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CallingConv::ID CC,
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unsigned &NumBytes,
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bool IsVarArg) {
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SmallVector<CCValAssign, 16> ArgLocs;
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CCState CCInfo(CC, IsVarArg, *FuncInfo.MF, TM, ArgLocs, *Context);
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CCInfo.AnalyzeCallOperands(ArgVTs, ArgFlags, CC_PPC64_ELF_FIS);
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// Bail out if we can't handle any of the arguments.
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for (unsigned I = 0, E = ArgLocs.size(); I != E; ++I) {
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CCValAssign &VA = ArgLocs[I];
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MVT ArgVT = ArgVTs[VA.getValNo()];
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// Skip vector arguments for now, as well as long double and
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// uint128_t, and anything that isn't passed in a register.
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if (ArgVT.isVector() || ArgVT.getSizeInBits() > 64 ||
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!VA.isRegLoc() || VA.needsCustom())
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return false;
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// Skip bit-converted arguments for now.
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if (VA.getLocInfo() == CCValAssign::BCvt)
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return false;
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}
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// Get a count of how many bytes are to be pushed onto the stack.
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NumBytes = CCInfo.getNextStackOffset();
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// Issue CALLSEQ_START.
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BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
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TII.get(TII.getCallFrameSetupOpcode()))
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.addImm(NumBytes);
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// Prepare to assign register arguments. Every argument uses up a
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// GPR protocol register even if it's passed in a floating-point
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// register.
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unsigned NextGPR = PPC::X3;
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unsigned NextFPR = PPC::F1;
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// Process arguments.
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for (unsigned I = 0, E = ArgLocs.size(); I != E; ++I) {
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CCValAssign &VA = ArgLocs[I];
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unsigned Arg = ArgRegs[VA.getValNo()];
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MVT ArgVT = ArgVTs[VA.getValNo()];
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// Handle argument promotion and bitcasts.
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switch (VA.getLocInfo()) {
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default:
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llvm_unreachable("Unknown loc info!");
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case CCValAssign::Full:
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break;
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case CCValAssign::SExt: {
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MVT DestVT = VA.getLocVT();
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const TargetRegisterClass *RC =
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(DestVT == MVT::i64) ? &PPC::G8RCRegClass : &PPC::GPRCRegClass;
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unsigned TmpReg = createResultReg(RC);
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if (!PPCEmitIntExt(ArgVT, Arg, DestVT, TmpReg, /*IsZExt*/false))
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llvm_unreachable("Failed to emit a sext!");
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ArgVT = DestVT;
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Arg = TmpReg;
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break;
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}
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case CCValAssign::AExt:
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case CCValAssign::ZExt: {
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MVT DestVT = VA.getLocVT();
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const TargetRegisterClass *RC =
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(DestVT == MVT::i64) ? &PPC::G8RCRegClass : &PPC::GPRCRegClass;
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unsigned TmpReg = createResultReg(RC);
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if (!PPCEmitIntExt(ArgVT, Arg, DestVT, TmpReg, /*IsZExt*/true))
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llvm_unreachable("Failed to emit a zext!");
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ArgVT = DestVT;
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Arg = TmpReg;
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break;
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}
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case CCValAssign::BCvt: {
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// FIXME: Not yet handled.
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llvm_unreachable("Should have bailed before getting here!");
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break;
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}
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}
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// Copy this argument to the appropriate register.
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unsigned ArgReg;
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if (ArgVT == MVT::f32 || ArgVT == MVT::f64) {
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ArgReg = NextFPR++;
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++NextGPR;
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} else
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ArgReg = NextGPR++;
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BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
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ArgReg).addReg(Arg);
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RegArgs.push_back(ArgReg);
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}
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return true;
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}
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// For a call that we've determined we can fast-select, finish the
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// call sequence and generate a copy to obtain the return value (if any).
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void PPCFastISel::finishCall(MVT RetVT, SmallVectorImpl<unsigned> &UsedRegs,
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const Instruction *I, CallingConv::ID CC,
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unsigned &NumBytes, bool IsVarArg) {
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// Issue CallSEQ_END.
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BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
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TII.get(TII.getCallFrameDestroyOpcode()))
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.addImm(NumBytes).addImm(0);
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// Next, generate a copy to obtain the return value.
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// FIXME: No multi-register return values yet, though I don't foresee
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// any real difficulties there.
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if (RetVT != MVT::isVoid) {
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SmallVector<CCValAssign, 16> RVLocs;
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CCState CCInfo(CC, IsVarArg, *FuncInfo.MF, TM, RVLocs, *Context);
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CCInfo.AnalyzeCallResult(RetVT, RetCC_PPC64_ELF_FIS);
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CCValAssign &VA = RVLocs[0];
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assert(RVLocs.size() == 1 && "No support for multi-reg return values!");
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assert(VA.isRegLoc() && "Can only return in registers!");
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MVT DestVT = VA.getValVT();
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MVT CopyVT = DestVT;
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// Ints smaller than a register still arrive in a full 64-bit
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// register, so make sure we recognize this.
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if (RetVT == MVT::i8 || RetVT == MVT::i16 || RetVT == MVT::i32)
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CopyVT = MVT::i64;
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unsigned SourcePhysReg = VA.getLocReg();
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unsigned ResultReg;
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if (RetVT == CopyVT) {
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const TargetRegisterClass *CpyRC = TLI.getRegClassFor(CopyVT);
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ResultReg = createResultReg(CpyRC);
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BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
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TII.get(TargetOpcode::COPY), ResultReg)
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.addReg(SourcePhysReg);
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// If necessary, round the floating result to single precision.
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} else if (CopyVT == MVT::f64) {
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ResultReg = createResultReg(TLI.getRegClassFor(RetVT));
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BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(PPC::FRSP),
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ResultReg).addReg(SourcePhysReg);
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// If only the low half of a general register is needed, generate
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// a GPRC copy instead of a G8RC copy. (EXTRACT_SUBREG can't be
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// used along the fast-isel path (not lowered), and downstream logic
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// also doesn't like a direct subreg copy on a physical reg.)
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} else if (RetVT == MVT::i8 || RetVT == MVT::i16 || RetVT == MVT::i32) {
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ResultReg = createResultReg(&PPC::GPRCRegClass);
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// Convert physical register from G8RC to GPRC.
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SourcePhysReg -= PPC::X0 - PPC::R0;
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BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
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TII.get(TargetOpcode::COPY), ResultReg)
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.addReg(SourcePhysReg);
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}
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UsedRegs.push_back(SourcePhysReg);
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UpdateValueMap(I, ResultReg);
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}
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}
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// Attempt to fast-select a call instruction.
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bool PPCFastISel::SelectCall(const Instruction *I) {
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const CallInst *CI = cast<CallInst>(I);
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const Value *Callee = CI->getCalledValue();
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// Can't handle inline asm.
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if (isa<InlineAsm>(Callee))
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return false;
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// Allow SelectionDAG isel to handle tail calls.
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if (CI->isTailCall())
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return false;
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// Obtain calling convention.
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ImmutableCallSite CS(CI);
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CallingConv::ID CC = CS.getCallingConv();
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PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType());
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FunctionType *FTy = cast<FunctionType>(PT->getElementType());
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bool IsVarArg = FTy->isVarArg();
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// Not ready for varargs yet.
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if (IsVarArg)
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return false;
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// Handle simple calls for now, with legal return types and
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// those that can be extended.
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Type *RetTy = I->getType();
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MVT RetVT;
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if (RetTy->isVoidTy())
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RetVT = MVT::isVoid;
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else if (!isTypeLegal(RetTy, RetVT) && RetVT != MVT::i16 &&
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RetVT != MVT::i8)
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return false;
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// FIXME: No multi-register return values yet.
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if (RetVT != MVT::isVoid && RetVT != MVT::i8 && RetVT != MVT::i16 &&
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RetVT != MVT::i32 && RetVT != MVT::i64 && RetVT != MVT::f32 &&
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RetVT != MVT::f64) {
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SmallVector<CCValAssign, 16> RVLocs;
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CCState CCInfo(CC, IsVarArg, *FuncInfo.MF, TM, RVLocs, *Context);
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CCInfo.AnalyzeCallResult(RetVT, RetCC_PPC64_ELF_FIS);
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if (RVLocs.size() > 1)
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return false;
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}
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// Bail early if more than 8 arguments, as we only currently
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// handle arguments passed in registers.
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unsigned NumArgs = CS.arg_size();
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if (NumArgs > 8)
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return false;
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// Set up the argument vectors.
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SmallVector<Value*, 8> Args;
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SmallVector<unsigned, 8> ArgRegs;
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SmallVector<MVT, 8> ArgVTs;
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SmallVector<ISD::ArgFlagsTy, 8> ArgFlags;
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Args.reserve(NumArgs);
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ArgRegs.reserve(NumArgs);
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ArgVTs.reserve(NumArgs);
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ArgFlags.reserve(NumArgs);
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for (ImmutableCallSite::arg_iterator II = CS.arg_begin(), IE = CS.arg_end();
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II != IE; ++II) {
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// FIXME: ARM does something for intrinsic calls here, check into that.
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unsigned AttrIdx = II - CS.arg_begin() + 1;
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// Only handle easy calls for now. It would be reasonably easy
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// to handle <= 8-byte structures passed ByVal in registers, but we
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// have to ensure they are right-justified in the register.
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if (CS.paramHasAttr(AttrIdx, Attribute::InReg) ||
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CS.paramHasAttr(AttrIdx, Attribute::StructRet) ||
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CS.paramHasAttr(AttrIdx, Attribute::Nest) ||
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CS.paramHasAttr(AttrIdx, Attribute::ByVal))
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return false;
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ISD::ArgFlagsTy Flags;
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if (CS.paramHasAttr(AttrIdx, Attribute::SExt))
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Flags.setSExt();
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if (CS.paramHasAttr(AttrIdx, Attribute::ZExt))
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Flags.setZExt();
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Type *ArgTy = (*II)->getType();
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MVT ArgVT;
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if (!isTypeLegal(ArgTy, ArgVT) && ArgVT != MVT::i16 && ArgVT != MVT::i8)
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return false;
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if (ArgVT.isVector())
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return false;
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unsigned Arg = getRegForValue(*II);
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if (Arg == 0)
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return false;
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unsigned OriginalAlignment = TD.getABITypeAlignment(ArgTy);
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Flags.setOrigAlign(OriginalAlignment);
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Args.push_back(*II);
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ArgRegs.push_back(Arg);
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ArgVTs.push_back(ArgVT);
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ArgFlags.push_back(Flags);
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}
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// Process the arguments.
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SmallVector<unsigned, 8> RegArgs;
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unsigned NumBytes;
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if (!processCallArgs(Args, ArgRegs, ArgVTs, ArgFlags,
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RegArgs, CC, NumBytes, IsVarArg))
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return false;
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// FIXME: No handling for function pointers yet. This requires
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// implementing the function descriptor (OPD) setup.
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const GlobalValue *GV = dyn_cast<GlobalValue>(Callee);
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if (!GV)
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return false;
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// Build direct call with NOP for TOC restore.
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// FIXME: We can and should optimize away the NOP for local calls.
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MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
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TII.get(PPC::BL8_NOP));
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// Add callee.
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MIB.addGlobalAddress(GV);
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// Add implicit physical register uses to the call.
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for (unsigned II = 0, IE = RegArgs.size(); II != IE; ++II)
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MIB.addReg(RegArgs[II], RegState::Implicit);
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// Add a register mask with the call-preserved registers. Proper
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// defs for return values will be added by setPhysRegsDeadExcept().
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MIB.addRegMask(TRI.getCallPreservedMask(CC));
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// Finish off the call including any return values.
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SmallVector<unsigned, 4> UsedRegs;
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finishCall(RetVT, UsedRegs, I, CC, NumBytes, IsVarArg);
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// Set all unused physregs defs as dead.
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static_cast<MachineInstr *>(MIB)->setPhysRegsDeadExcept(UsedRegs, TRI);
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return true;
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}
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// Attempt to fast-select a return instruction.
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bool PPCFastISel::SelectRet(const Instruction *I) {
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@ -1414,6 +1736,10 @@ bool PPCFastISel::TargetSelectInstruction(const Instruction *I) {
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return SelectBinaryIntOp(I, ISD::OR);
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case Instruction::Sub:
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return SelectBinaryIntOp(I, ISD::SUB);
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case Instruction::Call:
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if (dyn_cast<IntrinsicInst>(I))
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return false;
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return SelectCall(I);
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case Instruction::Ret:
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return SelectRet(I);
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case Instruction::ZExt:
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@ -1490,7 +1816,6 @@ unsigned PPCFastISel::PPCMaterializeGV(const GlobalValue *GV, MVT VT) {
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// If GV is an alias, use the aliasee for determining thread-locality.
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if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV))
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GVar = dyn_cast_or_null<GlobalVariable>(GA->resolveAliasedGlobal(false));
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assert((GVar || isa<Function>(GV)) && "Unexpected GV subclass!");
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}
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// FIXME: We don't yet handle the complexity of TLS.
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@ -1813,8 +1813,7 @@ SDValue PPCTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG,
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// Function whose sole purpose is to kill compiler warnings
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// stemming from unused functions included from PPCGenCallingConv.inc.
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CCAssignFn *PPCTargetLowering::useFastISelCCs(unsigned Flag) const {
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/* One of these will be CC_PPC64_ELF_FIS in a future patch. */
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return Flag ? RetCC_PPC64_ELF_FIS : RetCC_PPC64_ELF_FIS;
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return Flag ? CC_PPC64_ELF_FIS : RetCC_PPC64_ELF_FIS;
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}
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bool llvm::CC_PPC32_SVR4_Custom_Dummy(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
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132
test/CodeGen/PowerPC/fast-isel-call.ll
Normal file
132
test/CodeGen/PowerPC/fast-isel-call.ll
Normal file
@ -0,0 +1,132 @@
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; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 | FileCheck %s --check-prefix=ELF64
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define i32 @t1(i8 signext %a) nounwind {
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%1 = sext i8 %a to i32
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ret i32 %1
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}
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define i32 @t2(i8 zeroext %a) nounwind {
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%1 = zext i8 %a to i32
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ret i32 %1
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}
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define i32 @t3(i16 signext %a) nounwind {
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%1 = sext i16 %a to i32
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ret i32 %1
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}
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define i32 @t4(i16 zeroext %a) nounwind {
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%1 = zext i16 %a to i32
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ret i32 %1
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}
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|
||||
define void @foo(i8 %a, i16 %b) nounwind {
|
||||
; ELF64: foo
|
||||
%1 = call i32 @t1(i8 signext %a)
|
||||
; ELF64: extsb
|
||||
%2 = call i32 @t2(i8 zeroext %a)
|
||||
; ELF64: rldicl {{[0-9]+}}, {{[0-9]+}}, 0, 56
|
||||
%3 = call i32 @t3(i16 signext %b)
|
||||
; ELF64: extsh
|
||||
%4 = call i32 @t4(i16 zeroext %b)
|
||||
; ELF64: rldicl {{[0-9]+}}, {{[0-9]+}}, 0, 48
|
||||
|
||||
;; A few test to check materialization
|
||||
%5 = call i32 @t2(i8 zeroext 255)
|
||||
; ELF64: rldicl {{[0-9]+}}, {{[0-9]+}}, 0, 56
|
||||
%6 = call i32 @t4(i16 zeroext 65535)
|
||||
; ELF64: rldicl {{[0-9]+}}, {{[0-9]+}}, 0, 48
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @foo2() nounwind {
|
||||
%1 = call signext i16 @t5()
|
||||
%2 = call zeroext i16 @t6()
|
||||
%3 = call signext i8 @t7()
|
||||
%4 = call zeroext i8 @t8()
|
||||
ret void
|
||||
}
|
||||
|
||||
declare signext i16 @t5();
|
||||
declare zeroext i16 @t6();
|
||||
declare signext i8 @t7();
|
||||
declare zeroext i8 @t8();
|
||||
|
||||
define i32 @t10(i32 %argc, i8** nocapture %argv) {
|
||||
entry:
|
||||
; ELF64: t10
|
||||
%call = call i32 @bar(i8 zeroext 0, i8 zeroext -8, i8 zeroext -69, i8 zeroext 28, i8 zeroext 40, i8 zeroext -70)
|
||||
; ELF64: li 3, 0
|
||||
; ELF64: li 4, 248
|
||||
; ELF64: li 5, 187
|
||||
; ELF64: li 6, 28
|
||||
; ELF64: li 7, 40
|
||||
; ELF64: li 8, 186
|
||||
; ELF64: rldicl 3, 3, 0, 56
|
||||
; ELF64: rldicl 4, 4, 0, 56
|
||||
; ELF64: rldicl 5, 5, 0, 56
|
||||
; ELF64: rldicl 6, 6, 0, 56
|
||||
; ELF64: rldicl 7, 7, 0, 56
|
||||
; ELF64: rldicl 8, 8, 0, 56
|
||||
ret i32 0
|
||||
}
|
||||
|
||||
declare i32 @bar(i8 zeroext, i8 zeroext, i8 zeroext, i8 zeroext, i8 zeroext, i8 zeroext)
|
||||
|
||||
define i32 @bar0(i32 %i) nounwind {
|
||||
ret i32 0
|
||||
}
|
||||
|
||||
; Function pointers are not yet implemented.
|
||||
;define void @foo3() uwtable {
|
||||
; %fptr = alloca i32 (i32)*, align 8
|
||||
; store i32 (i32)* @bar0, i32 (i32)** %fptr, align 8
|
||||
; %1 = load i32 (i32)** %fptr, align 8
|
||||
; %call = call i32 %1(i32 0)
|
||||
; ret void
|
||||
;}
|
||||
|
||||
; Intrinsic calls not yet implemented, and udiv isn't one for PPC anyway.
|
||||
;define i32 @LibCall(i32 %a, i32 %b) {
|
||||
;entry:
|
||||
; %tmp1 = udiv i32 %a, %b ; <i32> [#uses=1]
|
||||
; ret i32 %tmp1
|
||||
;}
|
||||
|
||||
declare void @float_foo(float %f) ssp
|
||||
|
||||
define void @float_const() ssp {
|
||||
entry:
|
||||
; ELF64: float_const
|
||||
call void @float_foo(float 0x401C666660000000)
|
||||
; ELF64: addis [[REG:[0-9]+]], 2, .LCPI[[SUF:[0-9_]+]]@toc@ha
|
||||
; ELF64: lfs 1, .LCPI[[SUF]]@toc@l([[REG]])
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @float_reg(float %dummy, float %f) ssp {
|
||||
entry:
|
||||
; ELF64: float_reg
|
||||
call void @float_foo(float %f)
|
||||
; ELF64: fmr 1, 2
|
||||
ret void
|
||||
}
|
||||
|
||||
declare void @double_foo(double %d) ssp
|
||||
|
||||
define void @double_const() ssp {
|
||||
entry:
|
||||
; ELF64: double_const
|
||||
call void @double_foo(double 0x1397723CCABD0000401C666660000000)
|
||||
; ELF64: addis [[REG2:[0-9]+]], 2, .LCPI[[SUF2:[0-9_]+]]@toc@ha
|
||||
; ELF64: lfd 1, .LCPI[[SUF2]]@toc@l([[REG2]])
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @double_reg(double %dummy, double %d) ssp {
|
||||
entry:
|
||||
; ELF64: double_reg
|
||||
call void @double_foo(double %d)
|
||||
; ELF64: fmr 1, 2
|
||||
ret void
|
||||
}
|
||||
@ -4,6 +4,40 @@
|
||||
@b = global i16 2, align 2
|
||||
@c = global i32 4, align 4
|
||||
|
||||
define void @t1() nounwind uwtable ssp {
|
||||
; ELF64: t1
|
||||
%1 = load i8* @a, align 1
|
||||
call void @foo1(i8 zeroext %1)
|
||||
; ELF64: lbz
|
||||
; ELF64-NOT: rldicl
|
||||
; ELF64-NOT: rlwinm
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @t2() nounwind uwtable ssp {
|
||||
; ELF64: t2
|
||||
%1 = load i16* @b, align 2
|
||||
call void @foo2(i16 zeroext %1)
|
||||
; ELF64: lhz
|
||||
; ELF64-NOT: rldicl
|
||||
; ELF64-NOT: rlwinm
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @t2a() nounwind uwtable ssp {
|
||||
; ELF64: t2a
|
||||
%1 = load i32* @c, align 4
|
||||
call void @foo3(i32 zeroext %1)
|
||||
; ELF64: lwz
|
||||
; ELF64-NOT: rldicl
|
||||
; ELF64-NOT: rlwinm
|
||||
ret void
|
||||
}
|
||||
|
||||
declare void @foo1(i8 zeroext)
|
||||
declare void @foo2(i16 zeroext)
|
||||
declare void @foo3(i32 zeroext)
|
||||
|
||||
define i32 @t3() nounwind uwtable ssp {
|
||||
; ELF64: t3
|
||||
%1 = load i8* @a, align 1
|
||||
|
||||
Loading…
Reference in New Issue
Block a user