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- Add subtarget feature -mattr=+db which determine whether an ARM cpu has the

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memory and synchronization barrier dmb and dsb instructions.
- Change instruction names to something more sensible (matching name of actual
  instructions).
- Added tests for memory barrier codegen.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110785 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng
2010-08-11 06:22:01 +00:00
parent 3483acabf0
commit 11db068721
9 changed files with 88 additions and 55 deletions
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2
lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp
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@ -493,7 +493,7 @@ static inline ARM_AM::AMSubMode getAMSubModeForBits(unsigned bits) {
static bool DisassemblePseudo(MCInst &MI, unsigned Opcode, uint32_t insn,
unsigned short NumOps, unsigned &NumOpsAdded, BO) {
if (Opcode == ARM::Int_MemBarrierV7 || Opcode == ARM::Int_SyncBarrierV7)
if (Opcode == ARM::DMBsy || Opcode == ARM::DSBsy)
return true;
assert(0 && "Unexpected pseudo instruction!");