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[x86] Merge the interesting test cases from blend-msb.ll into

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vector-blend.ll and remove the former.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218814 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chandler Carruth 2014-10-01 20:56:57 +00:00
parent ccee7a87e0
commit 11e1c61b86
2 changed files with 18 additions and 40 deletions
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40
test/CodeGen/X86/blend-msb.ll
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@ -1,40 +0,0 @@
; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=corei7 -mattr=+sse4.1 | FileCheck %s
; Verify that we produce movss instead of blendvps when possible.
;CHECK-LABEL: vsel_float:
;CHECK-NOT: blend
;CHECK: movss
;CHECK: ret
define <4 x float> @vsel_float(<4 x float> %v1, <4 x float> %v2) {
%vsel = select <4 x i1> <i1 true, i1 false, i1 false, i1 false>, <4 x float> %v1, <4 x float> %v2
ret <4 x float> %vsel
}
;CHECK-LABEL: vsel_4xi8:
;CHECK-NOT: blend
;CHECK: movss
;CHECK: ret
define <4 x i8> @vsel_4xi8(<4 x i8> %v1, <4 x i8> %v2) {
%vsel = select <4 x i1> <i1 true, i1 false, i1 false, i1 false>, <4 x i8> %v1, <4 x i8> %v2
ret <4 x i8> %vsel
}
;CHECK-LABEL: vsel_8xi16:
; The select mask is
; <i1 true, i1 false, i1 false, i1 false, i1 true, i1 false, i1 false, i1 false>
; which translates into the boolean mask (big endian representation):
; 00010001 = 17.
; '1' means takes the first argument, '0' means takes the second argument.
; This is the opposite of the intel syntax, thus we expect
; the inverted mask: 11101110 = 238.
; According to the ABI:
; v1 is in xmm0 => first argument is xmm0.
; v2 is in xmm1 => second argument is xmm1.
;CHECK: pblendw $238, %xmm1, %xmm0
;CHECK: ret
define <8 x i16> @vsel_8xi16(<8 x i16> %v1, <8 x i16> %v2) {
%vsel = select <8 x i1> <i1 true, i1 false, i1 false, i1 false, i1 true, i1 false, i1 false, i1 false>, <8 x i16> %v1, <8 x i16> %v2
ret <8 x i16> %vsel
}

18
test/CodeGen/X86/vector-blend.ll
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@ -11,6 +11,15 @@ define <4 x float> @vsel_float(<4 x float> %v1, <4 x float> %v2) {
ret <4 x float> %vsel
}
define <4 x float> @vsel_float2(<4 x float> %v1, <4 x float> %v2) {
; CHECK-LABEL: vsel_float2:
; CHECK: ## BB#0:
; CHECK-NEXT: vmovss %xmm0, %xmm1, %xmm0
; CHECK-NEXT: retq
%vsel = select <4 x i1> <i1 true, i1 false, i1 false, i1 false>, <4 x float> %v1, <4 x float> %v2
ret <4 x float> %vsel
}
define <4 x i32> @vsel_i32(<4 x i32> %v1, <4 x i32> %v2) {
; CHECK-LABEL: vsel_i32:
; CHECK: ## BB#0:
@ -38,6 +47,15 @@ define <2 x i64> @vsel_i64(<2 x i64> %v1, <2 x i64> %v2) {
ret <2 x i64> %vsel
}
define <8 x i16> @vsel_8xi16(<8 x i16> %v1, <8 x i16> %v2) {
; CHECK-LABEL: vsel_8xi16:
; CHECK: ## BB#0:
; CHECK-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3],xmm0[4],xmm1[5,6,7]
; CHECK-NEXT: retq
%vsel = select <8 x i1> <i1 true, i1 false, i1 false, i1 false, i1 true, i1 false, i1 false, i1 false>, <8 x i16> %v1, <8 x i16> %v2
ret <8 x i16> %vsel
}
define <16 x i8> @vsel_i8(<16 x i8> %v1, <16 x i8> %v2) {
; CHECK-LABEL: vsel_i8:
; CHECK: ## BB#0: