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Fix handling of 'load' nodes.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105269 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Kalle Raiskila 2010-06-01 13:34:47 +00:00
parent 21330544df
commit 11fe24624a
2 changed files with 15 additions and 8 deletions
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10
lib/Target/CellSPU/SPUISelDAGToDAG.cpp
View File

@ -611,13 +611,7 @@ SPUDAGToDAGISel::DFormAddressPredicate(SDNode *Op, SDValue N, SDValue &Base,
if (OpOpc == ISD::STORE || OpOpc == ISD::LOAD) { if (OpOpc == ISD::STORE || OpOpc == ISD::LOAD) {
// Direct load/store without getelementptr // Direct load/store without getelementptr
SDValue Addr, Offs; SDValue Offs;
// Get the register from CopyFromReg
if (Opc == ISD::CopyFromReg)
Addr = N.getOperand(1);
else
Addr = N; // Register
Offs = ((OpOpc == ISD::STORE) ? Op->getOperand(3) : Op->getOperand(2)); Offs = ((OpOpc == ISD::STORE) ? Op->getOperand(3) : Op->getOperand(2));
@ -626,7 +620,7 @@ SPUDAGToDAGISel::DFormAddressPredicate(SDNode *Op, SDValue N, SDValue &Base,
Offs = CurDAG->getTargetConstant(0, Offs.getValueType()); Offs = CurDAG->getTargetConstant(0, Offs.getValueType());
Base = Offs; Base = Offs;
Index = Addr; Index = N;
return true; return true;
} }
} else { } else {

13
test/CodeGen/CellSPU/loads.ll
View File

@ -18,3 +18,16 @@ entry:
ret <4 x float> %tmp1 ret <4 x float> %tmp1
; CHECK: lqd $3, 16($3) ; CHECK: lqd $3, 16($3)
} }
declare <4 x i32>* @getv4f32ptr()
define <4 x i32> @func() {
;CHECK: brasl
;CHECK: lr {{\$[0-9]*, \$3}}
;CHECK: brasl
%rv1 = call <4 x i32>* @getv4f32ptr()
%rv2 = call <4 x i32>* @getv4f32ptr()
%rv3 = load <4 x i32>* %rv1
ret <4 x i32> %rv3
}