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fix some 80-col violations

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55571 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Gabor Greif 2008-08-30 19:29:20 +00:00
parent 07cabf6102
commit 12632d2222
1 changed files with 23 additions and 19 deletions
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42
lib/CodeGen/SelectionDAG/DAGCombiner.cpp
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@ -1196,7 +1196,8 @@ SDValue DAGCombiner::visitMUL(SDNode *N) {
N0.getNode()->hasOneUse()) { N0.getNode()->hasOneUse()) {
Sh = N0; Y = N1; Sh = N0; Y = N1;
} else if (N1.getOpcode() == ISD::SHL && } else if (N1.getOpcode() == ISD::SHL &&
isa<ConstantSDNode>(N1.getOperand(1)) && N1.getNode()->hasOneUse()) { isa<ConstantSDNode>(N1.getOperand(1)) &&
N1.getNode()->hasOneUse()) {
Sh = N1; Y = N0; Sh = N1; Y = N0;
} }
if (Sh.getNode()) { if (Sh.getNode()) {
@ -2068,10 +2069,8 @@ SDNode *DAGCombiner::MatchRotate(SDValue LHS, SDValue RHS) {
// (rotl x, (sub 32, y)) // (rotl x, (sub 32, y))
if (ConstantSDNode *SUBC = cast<ConstantSDNode>(RExtOp0.getOperand(0))) { if (ConstantSDNode *SUBC = cast<ConstantSDNode>(RExtOp0.getOperand(0))) {
if (SUBC->getAPIntValue() == OpSizeInBits) { if (SUBC->getAPIntValue() == OpSizeInBits) {
if (HasROTL) return DAG.getNode(HasROTL ? ISD::ROTL : ISD::ROTR, VT, LHSShiftArg,
return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt).getNode(); HasROTL ? LHSShiftAmt : RHSShiftAmt).getNode();
else
return DAG.getNode(ISD::ROTR, VT, LHSShiftArg, RHSShiftAmt).getNode();
} }
} }
} else if (LExtOp0.getOpcode() == ISD::SUB && } else if (LExtOp0.getOpcode() == ISD::SUB &&
@ -2082,10 +2081,8 @@ SDNode *DAGCombiner::MatchRotate(SDValue LHS, SDValue RHS) {
// (rotr x, (sub 32, y)) // (rotr x, (sub 32, y))
if (ConstantSDNode *SUBC = cast<ConstantSDNode>(LExtOp0.getOperand(0))) { if (ConstantSDNode *SUBC = cast<ConstantSDNode>(LExtOp0.getOperand(0))) {
if (SUBC->getAPIntValue() == OpSizeInBits) { if (SUBC->getAPIntValue() == OpSizeInBits) {
if (HasROTL) return DAG.getNode(ISD::ROTL, VT, LHSShiftArg,
return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, RHSShiftAmt).getNode(); HasROTL ? RHSShiftAmt : LHSShiftAmt).getNode();
else
return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt).getNode();
} }
} }
} }
@ -2144,7 +2141,8 @@ SDValue DAGCombiner::visitXOR(SDNode *N) {
} }
// fold (not (zext (setcc x, y))) -> (zext (not (setcc x, y))) // fold (not (zext (setcc x, y))) -> (zext (not (setcc x, y)))
if (N1C && N1C->getAPIntValue() == 1 && N0.getOpcode() == ISD::ZERO_EXTEND && if (N1C && N1C->getAPIntValue() == 1 && N0.getOpcode() == ISD::ZERO_EXTEND &&
N0.getNode()->hasOneUse() && isSetCCEquivalent(N0.getOperand(0), LHS, RHS, CC)){ N0.getNode()->hasOneUse() &&
isSetCCEquivalent(N0.getOperand(0), LHS, RHS, CC)){
SDValue V = N0.getOperand(0); SDValue V = N0.getOperand(0);
V = DAG.getNode(ISD::XOR, V.getValueType(), V, V = DAG.getNode(ISD::XOR, V.getValueType(), V,
DAG.getConstant(1, V.getValueType())); DAG.getConstant(1, V.getValueType()));
@ -2426,7 +2424,7 @@ SDValue DAGCombiner::visitSRA(SDNode *N) {
// If the shift is not a no-op (in which case this should be just a sign // If the shift is not a no-op (in which case this should be just a sign
// extend already), the truncated to type is legal, sign_extend is legal // extend already), the truncated to type is legal, sign_extend is legal
// on that type, and the the truncate to that type is both legal and free, // on that type, and the the truncate to that type is both legal and free,
// perform the transform. // perform the transform.
if (ShiftAmt && if (ShiftAmt &&
TLI.isOperationLegal(ISD::SIGN_EXTEND, TruncVT) && TLI.isOperationLegal(ISD::SIGN_EXTEND, TruncVT) &&
@ -2746,7 +2744,8 @@ static bool ExtendUsesToFormExtLoad(SDNode *N, SDValue N0,
TargetLowering &TLI) { TargetLowering &TLI) {
bool HasCopyToRegUses = false; bool HasCopyToRegUses = false;
bool isTruncFree = TLI.isTruncateFree(N->getValueType(0), N0.getValueType()); bool isTruncFree = TLI.isTruncateFree(N->getValueType(0), N0.getValueType());
for (SDNode::use_iterator UI = N0.getNode()->use_begin(), UE = N0.getNode()->use_end(); for (SDNode::use_iterator UI = N0.getNode()->use_begin(),
UE = N0.getNode()->use_end();
UI != UE; ++UI) { UI != UE; ++UI) {
SDNode *User = *UI; SDNode *User = *UI;
if (User == N) if (User == N)
@ -2916,7 +2915,8 @@ SDValue DAGCombiner::visitSIGN_EXTEND(SDNode *N) {
LN0->isVolatile(), LN0->isVolatile(),
LN0->getAlignment()); LN0->getAlignment());
CombineTo(N, ExtLoad); CombineTo(N, ExtLoad);
CombineTo(N0.getNode(), DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), CombineTo(N0.getNode(),
DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
ExtLoad.getValue(1)); ExtLoad.getValue(1));
return SDValue(N, 0); // Return N so it doesn't get rechecked! return SDValue(N, 0); // Return N so it doesn't get rechecked!
} }
@ -3041,7 +3041,8 @@ SDValue DAGCombiner::visitZERO_EXTEND(SDNode *N) {
LN0->isVolatile(), LN0->isVolatile(),
LN0->getAlignment()); LN0->getAlignment());
CombineTo(N, ExtLoad); CombineTo(N, ExtLoad);
CombineTo(N0.getNode(), DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), CombineTo(N0.getNode(),
DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
ExtLoad.getValue(1)); ExtLoad.getValue(1));
return SDValue(N, 0); // Return N so it doesn't get rechecked! return SDValue(N, 0); // Return N so it doesn't get rechecked!
} }
@ -3514,7 +3515,8 @@ SDValue DAGCombiner::visitBIT_CONVERT(SDNode *N) {
LN0->getSrcValue(), LN0->getSrcValueOffset(), LN0->getSrcValue(), LN0->getSrcValueOffset(),
LN0->isVolatile(), OrigAlign); LN0->isVolatile(), OrigAlign);
AddToWorkList(N); AddToWorkList(N);
CombineTo(N0.getNode(), DAG.getNode(ISD::BIT_CONVERT, N0.getValueType(), Load), CombineTo(N0.getNode(),
DAG.getNode(ISD::BIT_CONVERT, N0.getValueType(), Load),
Load.getValue(1)); Load.getValue(1));
return Load; return Load;
} }
@ -4037,7 +4039,8 @@ SDValue DAGCombiner::visitFP_EXTEND(SDNode *N) {
// Turn fp_extend(fp_round(X, 1)) -> x since the fp_round doesn't affect the // Turn fp_extend(fp_round(X, 1)) -> x since the fp_round doesn't affect the
// value of X. // value of X.
if (N0.getOpcode() == ISD::FP_ROUND && N0.getNode()->getConstantOperandVal(1) == 1){ if (N0.getOpcode() == ISD::FP_ROUND
&& N0.getNode()->getConstantOperandVal(1) == 1) {
SDValue In = N0.getOperand(0); SDValue In = N0.getOperand(0);
if (In.getValueType() == VT) return In; if (In.getValueType() == VT) return In;
if (VT.bitsLT(In.getValueType())) if (VT.bitsLT(In.getValueType()))
@ -4057,8 +4060,8 @@ SDValue DAGCombiner::visitFP_EXTEND(SDNode *N) {
LN0->isVolatile(), LN0->isVolatile(),
LN0->getAlignment()); LN0->getAlignment());
CombineTo(N, ExtLoad); CombineTo(N, ExtLoad);
CombineTo(N0.getNode(), DAG.getNode(ISD::FP_ROUND, N0.getValueType(), ExtLoad, CombineTo(N0.getNode(), DAG.getNode(ISD::FP_ROUND, N0.getValueType(),
DAG.getIntPtrConstant(1)), ExtLoad, DAG.getIntPtrConstant(1)),
ExtLoad.getValue(1)); ExtLoad.getValue(1));
return SDValue(N, 0); // Return N so it doesn't get rechecked! return SDValue(N, 0); // Return N so it doesn't get rechecked!
} }
@ -4772,7 +4775,8 @@ SDValue DAGCombiner::visitINSERT_VECTOR_ELT(SDNode *N) {
// vector with the inserted element. // vector with the inserted element.
if (InVec.getOpcode() == ISD::BUILD_VECTOR && isa<ConstantSDNode>(EltNo)) { if (InVec.getOpcode() == ISD::BUILD_VECTOR && isa<ConstantSDNode>(EltNo)) {
unsigned Elt = cast<ConstantSDNode>(EltNo)->getValue(); unsigned Elt = cast<ConstantSDNode>(EltNo)->getValue();
SmallVector<SDValue, 8> Ops(InVec.getNode()->op_begin(), InVec.getNode()->op_end()); SmallVector<SDValue, 8> Ops(InVec.getNode()->op_begin(),
InVec.getNode()->op_end());
if (Elt < Ops.size()) if (Elt < Ops.size())
Ops[Elt] = InVal; Ops[Elt] = InVal;
return DAG.getNode(ISD::BUILD_VECTOR, InVec.getValueType(), return DAG.getNode(ISD::BUILD_VECTOR, InVec.getValueType(),