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Fix a post-RA scheduling liveness bug. When a basic block is being

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scheduled in multiple regions, liveness data used by the
anti-dependence breaker is carried from one region to the next, however
the information reflects the state of the instructions before scheduling.
After scheduling, there may be new live range overlaps. Handle this by
pessimizing the liveness data carried between regions to the point where
it will be conservatively correct now matter how the earlier region is
scheduled. This fixes a miscompilation in 176.gcc with the post-RA
scheduler enabled.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66558 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Dan Gohman 2009-03-10 18:10:43 +00:00
parent 9200c89968
commit 1274ced8a3
1 changed files with 22 additions and 9 deletions
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31
lib/CodeGen/PostRASchedulerList.cpp
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@ -258,22 +258,19 @@ bool PostRAScheduler::runOnMachineFunction(MachineFunction &Fn) {
for (MachineBasicBlock::iterator I = Current; I != MBB->begin(); ) {
MachineInstr *MI = prior(I);
if (isSchedulingBoundary(MI, Fn)) {
if (I != Current) {
Scheduler.Run(MBB, I, Current, CurrentCount);
Scheduler.EmitSchedule();
}
Scheduler.Observe(MI, Count);
Scheduler.Run(MBB, I, Current, CurrentCount);
Scheduler.EmitSchedule();
Current = MI;
CurrentCount = Count - 1;
Scheduler.Observe(MI, CurrentCount);
}
I = MI;
--Count;
}
assert(Count == 0 && "Instruction count mismatch!");
if (MBB->begin() != Current) {
assert(CurrentCount != 0 && "Instruction count mismatch!");
Scheduler.Run(MBB, MBB->begin(), Current, CurrentCount);
}
assert(MBB->begin() == Current || CurrentCount != 0 &&
"Instruction count mismatch!");
Scheduler.Run(MBB, MBB->begin(), Current, CurrentCount);
Scheduler.EmitSchedule();
// Clean up register live-range state.
@ -392,6 +389,22 @@ void SchedulePostRATDList::Schedule() {
/// instruction, which will not be scheduled.
///
void SchedulePostRATDList::Observe(MachineInstr *MI, unsigned Count) {
assert(Count < InsertPosIndex && "Instruction index out of expected range!");
// Any register which was defined within the previous scheduling region
// may have been rescheduled and its lifetime may overlap with registers
// in ways not reflected in our current liveness state. For each such
// register, adjust the liveness state to be conservatively correct.
for (unsigned Reg = 0; Reg != TargetRegisterInfo::FirstVirtualRegister; ++Reg)
if (DefIndices[Reg] < InsertPosIndex && DefIndices[Reg] >= Count) {
assert(KillIndices[Reg] == ~0u && "Clobbered register is live!");
// Mark this register to be non-renamable.
Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1);
// Move the def index to the end of the previous region, to reflect
// that the def could theoretically have been scheduled at the end.
DefIndices[Reg] = InsertPosIndex;
}
PrescanInstruction(MI);
ScanInstruction(MI, Count);
}