mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2025-03-18 12:31:26 +00:00
[X86] Make isel select the shorter form of jump instructions instead of the long form.
The assembler backend will relax to the long form if necessary. This removes a swap from long form to short form in the MCInstLowering code. Selecting the long form used to be required by the old JIT. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225242 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
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@ -656,7 +656,7 @@ void X86AddressSanitizer32::InstrumentMemOperandSmall(
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Out, MCInstBuilder(X86::TEST8rr).addReg(ShadowRegI8).addReg(ShadowRegI8));
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MCSymbol *DoneSym = Ctx.CreateTempSymbol();
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const MCExpr *DoneExpr = MCSymbolRefExpr::Create(DoneSym, Ctx);
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EmitInstruction(Out, MCInstBuilder(X86::JE_4).addExpr(DoneExpr));
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EmitInstruction(Out, MCInstBuilder(X86::JE_1).addExpr(DoneExpr));
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EmitInstruction(Out, MCInstBuilder(X86::MOV32rr).addReg(ScratchRegI32).addReg(
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AddressRegI32));
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@ -690,7 +690,7 @@ void X86AddressSanitizer32::InstrumentMemOperandSmall(
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MCInstBuilder(X86::MOVSX32rr8).addReg(ShadowRegI32).addReg(ShadowRegI8));
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EmitInstruction(Out, MCInstBuilder(X86::CMP32rr).addReg(ScratchRegI32).addReg(
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ShadowRegI32));
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EmitInstruction(Out, MCInstBuilder(X86::JL_4).addExpr(DoneExpr));
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EmitInstruction(Out, MCInstBuilder(X86::JL_1).addExpr(DoneExpr));
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EmitCallAsanReport(AccessSize, IsWrite, Ctx, Out, RegCtx);
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EmitLabel(Out, DoneSym);
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@ -731,7 +731,7 @@ void X86AddressSanitizer32::InstrumentMemOperandLarge(
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}
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MCSymbol *DoneSym = Ctx.CreateTempSymbol();
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const MCExpr *DoneExpr = MCSymbolRefExpr::Create(DoneSym, Ctx);
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EmitInstruction(Out, MCInstBuilder(X86::JE_4).addExpr(DoneExpr));
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EmitInstruction(Out, MCInstBuilder(X86::JE_1).addExpr(DoneExpr));
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EmitCallAsanReport(AccessSize, IsWrite, Ctx, Out, RegCtx);
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EmitLabel(Out, DoneSym);
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@ -747,7 +747,7 @@ void X86AddressSanitizer32::InstrumentMOVSImpl(unsigned AccessSize,
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const MCExpr *DoneExpr = MCSymbolRefExpr::Create(DoneSym, Ctx);
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EmitInstruction(
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Out, MCInstBuilder(X86::TEST32rr).addReg(X86::ECX).addReg(X86::ECX));
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EmitInstruction(Out, MCInstBuilder(X86::JE_4).addExpr(DoneExpr));
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EmitInstruction(Out, MCInstBuilder(X86::JE_1).addExpr(DoneExpr));
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// Instrument first and last elements in src and dst range.
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InstrumentMOVSBase(X86::EDI /* DstReg */, X86::ESI /* SrcReg */,
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@ -927,7 +927,7 @@ void X86AddressSanitizer64::InstrumentMemOperandSmall(
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Out, MCInstBuilder(X86::TEST8rr).addReg(ShadowRegI8).addReg(ShadowRegI8));
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MCSymbol *DoneSym = Ctx.CreateTempSymbol();
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const MCExpr *DoneExpr = MCSymbolRefExpr::Create(DoneSym, Ctx);
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EmitInstruction(Out, MCInstBuilder(X86::JE_4).addExpr(DoneExpr));
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EmitInstruction(Out, MCInstBuilder(X86::JE_1).addExpr(DoneExpr));
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EmitInstruction(Out, MCInstBuilder(X86::MOV32rr).addReg(ScratchRegI32).addReg(
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AddressRegI32));
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@ -961,7 +961,7 @@ void X86AddressSanitizer64::InstrumentMemOperandSmall(
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MCInstBuilder(X86::MOVSX32rr8).addReg(ShadowRegI32).addReg(ShadowRegI8));
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EmitInstruction(Out, MCInstBuilder(X86::CMP32rr).addReg(ScratchRegI32).addReg(
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ShadowRegI32));
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EmitInstruction(Out, MCInstBuilder(X86::JL_4).addExpr(DoneExpr));
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EmitInstruction(Out, MCInstBuilder(X86::JL_1).addExpr(DoneExpr));
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EmitCallAsanReport(AccessSize, IsWrite, Ctx, Out, RegCtx);
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EmitLabel(Out, DoneSym);
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@ -1003,7 +1003,7 @@ void X86AddressSanitizer64::InstrumentMemOperandLarge(
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MCSymbol *DoneSym = Ctx.CreateTempSymbol();
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const MCExpr *DoneExpr = MCSymbolRefExpr::Create(DoneSym, Ctx);
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EmitInstruction(Out, MCInstBuilder(X86::JE_4).addExpr(DoneExpr));
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EmitInstruction(Out, MCInstBuilder(X86::JE_1).addExpr(DoneExpr));
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EmitCallAsanReport(AccessSize, IsWrite, Ctx, Out, RegCtx);
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EmitLabel(Out, DoneSym);
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@ -1019,7 +1019,7 @@ void X86AddressSanitizer64::InstrumentMOVSImpl(unsigned AccessSize,
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const MCExpr *DoneExpr = MCSymbolRefExpr::Create(DoneSym, Ctx);
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EmitInstruction(
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Out, MCInstBuilder(X86::TEST64rr).addReg(X86::RCX).addReg(X86::RCX));
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EmitInstruction(Out, MCInstBuilder(X86::JE_4).addExpr(DoneExpr));
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EmitInstruction(Out, MCInstBuilder(X86::JE_1).addExpr(DoneExpr));
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// Instrument first and last elements in src and dst range.
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InstrumentMOVSBase(X86::RDI /* DstReg */, X86::RSI /* SrcReg */,
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@ -1362,7 +1362,7 @@ bool X86FastISel::X86SelectBranch(const Instruction *I) {
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// X86 requires a second branch to handle UNE (and OEQ, which is mapped
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// to UNE above).
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if (NeedExtraBranch) {
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BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(X86::JP_4))
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BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(X86::JP_1))
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.addMBB(TrueMBB);
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}
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@ -1399,10 +1399,10 @@ bool X86FastISel::X86SelectBranch(const Instruction *I) {
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BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(TestOpc))
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.addReg(OpReg).addImm(1);
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unsigned JmpOpc = X86::JNE_4;
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unsigned JmpOpc = X86::JNE_1;
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if (FuncInfo.MBB->isLayoutSuccessor(TrueMBB)) {
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std::swap(TrueMBB, FalseMBB);
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JmpOpc = X86::JE_4;
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JmpOpc = X86::JE_1;
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}
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BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(JmpOpc))
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@ -1444,7 +1444,7 @@ bool X86FastISel::X86SelectBranch(const Instruction *I) {
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BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(X86::TEST8ri))
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.addReg(OpReg).addImm(1);
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BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(X86::JNE_4))
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BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(X86::JNE_1))
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.addMBB(TrueMBB);
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fastEmitBranch(FalseMBB, DbgLoc);
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uint32_t BranchWeight = 0;
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@ -1617,7 +1617,7 @@ X86FrameLowering::adjustForSegmentedStacks(MachineFunction &MF) const {
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// This jump is taken if SP >= (Stacklet Limit + Stack Space required).
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// It jumps to normal execution of the function body.
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BuildMI(checkMBB, DL, TII.get(X86::JA_4)).addMBB(&prologueMBB);
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BuildMI(checkMBB, DL, TII.get(X86::JA_1)).addMBB(&prologueMBB);
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// On 32 bit we first push the arguments size and then the frame size. On 64
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// bit, we pass the stack frame size in r10 and the argument size in r11.
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@ -1821,7 +1821,7 @@ void X86FrameLowering::adjustForHiPEPrologue(MachineFunction &MF) const {
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// SPLimitOffset is in a fixed heap location (pointed by BP).
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addRegOffset(BuildMI(stackCheckMBB, DL, TII.get(CMPop))
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.addReg(ScratchReg), PReg, false, SPLimitOffset);
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BuildMI(stackCheckMBB, DL, TII.get(X86::JAE_4)).addMBB(&prologueMBB);
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BuildMI(stackCheckMBB, DL, TII.get(X86::JAE_1)).addMBB(&prologueMBB);
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// Create new MBB for IncStack:
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BuildMI(incStackMBB, DL, TII.get(CALLop)).
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@ -1830,7 +1830,7 @@ void X86FrameLowering::adjustForHiPEPrologue(MachineFunction &MF) const {
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SPReg, false, -MaxStack);
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addRegOffset(BuildMI(incStackMBB, DL, TII.get(CMPop))
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.addReg(ScratchReg), PReg, false, SPLimitOffset);
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BuildMI(incStackMBB, DL, TII.get(X86::JLE_4)).addMBB(incStackMBB);
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BuildMI(incStackMBB, DL, TII.get(X86::JLE_1)).addMBB(incStackMBB);
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stackCheckMBB->addSuccessor(&prologueMBB, 99);
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stackCheckMBB->addSuccessor(incStackMBB, 1);
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@ -1891,8 +1891,8 @@ static bool HasNoSignedComparisonUses(SDNode *N) {
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case X86::SETEr: case X86::SETNEr: case X86::SETPr: case X86::SETNPr:
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case X86::SETAm: case X86::SETAEm: case X86::SETBm: case X86::SETBEm:
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case X86::SETEm: case X86::SETNEm: case X86::SETPm: case X86::SETNPm:
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case X86::JA_4: case X86::JAE_4: case X86::JB_4: case X86::JBE_4:
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case X86::JE_4: case X86::JNE_4: case X86::JP_4: case X86::JNP_4:
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case X86::JA_1: case X86::JAE_1: case X86::JB_1: case X86::JBE_1:
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case X86::JE_1: case X86::JNE_1: case X86::JP_1: case X86::JNP_1:
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case X86::CMOVA16rr: case X86::CMOVA16rm:
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case X86::CMOVA32rr: case X86::CMOVA32rm:
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case X86::CMOVA64rr: case X86::CMOVA64rm:
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@ -20527,7 +20527,7 @@ X86TargetLowering::EmitVAARG64WithCustomInserter(
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.setMemRefs(MMOBegin, MMOEnd);
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// Jump to endMBB
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BuildMI(offsetMBB, DL, TII->get(X86::JMP_4))
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BuildMI(offsetMBB, DL, TII->get(X86::JMP_1))
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.addMBB(endMBB);
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}
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@ -20641,7 +20641,7 @@ X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
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if (!Subtarget->isTargetWin64()) {
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// If %al is 0, branch around the XMM save block.
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BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
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BuildMI(MBB, DL, TII->get(X86::JE_4)).addMBB(EndMBB);
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BuildMI(MBB, DL, TII->get(X86::JE_1)).addMBB(EndMBB);
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MBB->addSuccessor(EndMBB);
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}
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@ -20845,7 +20845,7 @@ X86TargetLowering::EmitLoweredSegAlloca(MachineInstr *MI,
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BuildMI(BB, DL, TII->get(IsLP64 ? X86::CMP64mr:X86::CMP32mr))
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.addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg)
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.addReg(SPLimitVReg);
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BuildMI(BB, DL, TII->get(X86::JG_4)).addMBB(mallocMBB);
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BuildMI(BB, DL, TII->get(X86::JG_1)).addMBB(mallocMBB);
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// bumpMBB simply decreases the stack pointer, since we know the current
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// stacklet has enough space.
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@ -20853,7 +20853,7 @@ X86TargetLowering::EmitLoweredSegAlloca(MachineInstr *MI,
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.addReg(SPLimitVReg);
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BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), bumpSPPtrVReg)
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.addReg(SPLimitVReg);
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BuildMI(bumpMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
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BuildMI(bumpMBB, DL, TII->get(X86::JMP_1)).addMBB(continueMBB);
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// Calls into a routine in libgcc to allocate more space from the heap.
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const uint32_t *RegMask = MF->getTarget()
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@ -20892,7 +20892,7 @@ X86TargetLowering::EmitLoweredSegAlloca(MachineInstr *MI,
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BuildMI(mallocMBB, DL, TII->get(TargetOpcode::COPY), mallocPtrVReg)
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.addReg(IsLP64 ? X86::RAX : X86::EAX);
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BuildMI(mallocMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
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BuildMI(mallocMBB, DL, TII->get(X86::JMP_1)).addMBB(continueMBB);
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// Set up the CFG correctly.
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BB->addSuccessor(bumpMBB);
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@ -21171,7 +21171,7 @@ X86TargetLowering::emitEHSjLjSetJmp(MachineInstr *MI,
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.setMIFlag(MachineInstr::FrameSetup);
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}
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BuildMI(restoreMBB, DL, TII->get(X86::MOV32ri), restoreDstReg).addImm(1);
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BuildMI(restoreMBB, DL, TII->get(X86::JMP_4)).addMBB(sinkMBB);
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BuildMI(restoreMBB, DL, TII->get(X86::JMP_1)).addMBB(sinkMBB);
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restoreMBB->addSuccessor(sinkMBB);
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MI->eraseFromParent();
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@ -57,33 +57,32 @@ let isTerminator = 1, isReturn = 1, isBarrier = 1,
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// Unconditional branches.
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let isBarrier = 1, isBranch = 1, isTerminator = 1, SchedRW = [WriteJump] in {
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def JMP_4 : Ii32PCRel<0xE9, RawFrm, (outs), (ins brtarget:$dst),
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"jmp\t$dst", [(br bb:$dst)], IIC_JMP_REL>, OpSize32;
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def JMP_2 : Ii16PCRel<0xE9, RawFrm, (outs), (ins brtarget:$dst),
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"jmp\t$dst", [(br bb:$dst)], IIC_JMP_REL>, OpSize16,
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Requires<[In16BitMode]>;
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let hasSideEffects = 0 in
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def JMP_1 : Ii8PCRel<0xEB, RawFrm, (outs), (ins brtarget8:$dst),
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"jmp\t$dst", [], IIC_JMP_REL>;
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"jmp\t$dst", [(br bb:$dst)], IIC_JMP_REL>;
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let hasSideEffects = 0 in {
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def JMP_2 : Ii16PCRel<0xE9, RawFrm, (outs), (ins brtarget:$dst),
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"jmp\t$dst", [], IIC_JMP_REL>, OpSize16;
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def JMP_4 : Ii32PCRel<0xE9, RawFrm, (outs), (ins brtarget:$dst),
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"jmp\t$dst", [], IIC_JMP_REL>, OpSize32;
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}
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}
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// Conditional Branches.
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let isBranch = 1, isTerminator = 1, Uses = [EFLAGS], SchedRW = [WriteJump] in {
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multiclass ICBr<bits<8> opc1, bits<8> opc4, string asm, PatFrag Cond> {
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let hasSideEffects = 0 in
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def _1 : Ii8PCRel <opc1, RawFrm, (outs), (ins brtarget8:$dst), asm, [],
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IIC_Jcc>;
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def _2 : Ii16PCRel<opc4, RawFrm, (outs), (ins brtarget:$dst), asm,
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[(X86brcond bb:$dst, Cond, EFLAGS)], IIC_Jcc>, OpSize16,
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TB, Requires<[In16BitMode]>;
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def _4 : Ii32PCRel<opc4, RawFrm, (outs), (ins brtarget:$dst), asm,
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[(X86brcond bb:$dst, Cond, EFLAGS)], IIC_Jcc>, TB,
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OpSize32;
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def _1 : Ii8PCRel <opc1, RawFrm, (outs), (ins brtarget8:$dst), asm,
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[(X86brcond bb:$dst, Cond, EFLAGS)], IIC_Jcc>;
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let hasSideEffects = 0 in {
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def _2 : Ii16PCRel<opc4, RawFrm, (outs), (ins brtarget:$dst), asm,
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[], IIC_Jcc>, OpSize16, TB;
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def _4 : Ii32PCRel<opc4, RawFrm, (outs), (ins brtarget:$dst), asm,
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[], IIC_Jcc>, TB, OpSize32;
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}
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}
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}
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defm JO : ICBr<0x70, 0x80, "jo\t$dst" , X86_COND_O>;
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defm JNO : ICBr<0x71, 0x81, "jno\t$dst" , X86_COND_NO>;
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defm JNO : ICBr<0x71, 0x81, "jno\t$dst", X86_COND_NO>;
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defm JB : ICBr<0x72, 0x82, "jb\t$dst" , X86_COND_B>;
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defm JAE : ICBr<0x73, 0x83, "jae\t$dst", X86_COND_AE>;
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defm JE : ICBr<0x74, 0x84, "je\t$dst" , X86_COND_E>;
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@ -2723,22 +2723,22 @@ bool X86InstrInfo::findCommutedOpIndices(MachineInstr *MI, unsigned &SrcOpIdx1,
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static X86::CondCode getCondFromBranchOpc(unsigned BrOpc) {
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switch (BrOpc) {
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default: return X86::COND_INVALID;
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case X86::JE_4: return X86::COND_E;
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case X86::JNE_4: return X86::COND_NE;
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case X86::JL_4: return X86::COND_L;
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case X86::JLE_4: return X86::COND_LE;
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case X86::JG_4: return X86::COND_G;
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case X86::JGE_4: return X86::COND_GE;
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case X86::JB_4: return X86::COND_B;
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case X86::JBE_4: return X86::COND_BE;
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case X86::JA_4: return X86::COND_A;
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case X86::JAE_4: return X86::COND_AE;
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case X86::JS_4: return X86::COND_S;
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case X86::JNS_4: return X86::COND_NS;
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case X86::JP_4: return X86::COND_P;
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case X86::JNP_4: return X86::COND_NP;
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case X86::JO_4: return X86::COND_O;
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case X86::JNO_4: return X86::COND_NO;
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case X86::JE_1: return X86::COND_E;
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case X86::JNE_1: return X86::COND_NE;
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case X86::JL_1: return X86::COND_L;
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case X86::JLE_1: return X86::COND_LE;
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case X86::JG_1: return X86::COND_G;
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case X86::JGE_1: return X86::COND_GE;
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case X86::JB_1: return X86::COND_B;
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case X86::JBE_1: return X86::COND_BE;
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case X86::JA_1: return X86::COND_A;
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case X86::JAE_1: return X86::COND_AE;
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case X86::JS_1: return X86::COND_S;
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case X86::JNS_1: return X86::COND_NS;
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case X86::JP_1: return X86::COND_P;
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case X86::JNP_1: return X86::COND_NP;
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case X86::JO_1: return X86::COND_O;
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case X86::JNO_1: return X86::COND_NO;
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}
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}
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@ -2823,22 +2823,22 @@ X86::CondCode X86::getCondFromCMovOpc(unsigned Opc) {
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unsigned X86::GetCondBranchFromCond(X86::CondCode CC) {
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switch (CC) {
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default: llvm_unreachable("Illegal condition code!");
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case X86::COND_E: return X86::JE_4;
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case X86::COND_NE: return X86::JNE_4;
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case X86::COND_L: return X86::JL_4;
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case X86::COND_LE: return X86::JLE_4;
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case X86::COND_G: return X86::JG_4;
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case X86::COND_GE: return X86::JGE_4;
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case X86::COND_B: return X86::JB_4;
|
||||
case X86::COND_BE: return X86::JBE_4;
|
||||
case X86::COND_A: return X86::JA_4;
|
||||
case X86::COND_AE: return X86::JAE_4;
|
||||
case X86::COND_S: return X86::JS_4;
|
||||
case X86::COND_NS: return X86::JNS_4;
|
||||
case X86::COND_P: return X86::JP_4;
|
||||
case X86::COND_NP: return X86::JNP_4;
|
||||
case X86::COND_O: return X86::JO_4;
|
||||
case X86::COND_NO: return X86::JNO_4;
|
||||
case X86::COND_E: return X86::JE_1;
|
||||
case X86::COND_NE: return X86::JNE_1;
|
||||
case X86::COND_L: return X86::JL_1;
|
||||
case X86::COND_LE: return X86::JLE_1;
|
||||
case X86::COND_G: return X86::JG_1;
|
||||
case X86::COND_GE: return X86::JGE_1;
|
||||
case X86::COND_B: return X86::JB_1;
|
||||
case X86::COND_BE: return X86::JBE_1;
|
||||
case X86::COND_A: return X86::JA_1;
|
||||
case X86::COND_AE: return X86::JAE_1;
|
||||
case X86::COND_S: return X86::JS_1;
|
||||
case X86::COND_NS: return X86::JNS_1;
|
||||
case X86::COND_P: return X86::JP_1;
|
||||
case X86::COND_NP: return X86::JNP_1;
|
||||
case X86::COND_O: return X86::JO_1;
|
||||
case X86::COND_NO: return X86::JNO_1;
|
||||
}
|
||||
}
|
||||
|
||||
@ -2996,7 +2996,7 @@ bool X86InstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
|
||||
return true;
|
||||
|
||||
// Handle unconditional branches.
|
||||
if (I->getOpcode() == X86::JMP_4) {
|
||||
if (I->getOpcode() == X86::JMP_1) {
|
||||
UnCondBrIter = I;
|
||||
|
||||
if (!AllowModify) {
|
||||
@ -3058,7 +3058,7 @@ bool X86InstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
|
||||
|
||||
BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(JNCC))
|
||||
.addMBB(UnCondBrIter->getOperand(0).getMBB());
|
||||
BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(X86::JMP_4))
|
||||
BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(X86::JMP_1))
|
||||
.addMBB(TargetBB);
|
||||
|
||||
OldInst->eraseFromParent();
|
||||
@ -3123,7 +3123,7 @@ unsigned X86InstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
|
||||
--I;
|
||||
if (I->isDebugValue())
|
||||
continue;
|
||||
if (I->getOpcode() != X86::JMP_4 &&
|
||||
if (I->getOpcode() != X86::JMP_1 &&
|
||||
getCondFromBranchOpc(I->getOpcode()) == X86::COND_INVALID)
|
||||
break;
|
||||
// Remove the branch.
|
||||
@ -3148,7 +3148,7 @@ X86InstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
|
||||
if (Cond.empty()) {
|
||||
// Unconditional branch?
|
||||
assert(!FBB && "Unconditional branch with multiple successors!");
|
||||
BuildMI(&MBB, DL, get(X86::JMP_4)).addMBB(TBB);
|
||||
BuildMI(&MBB, DL, get(X86::JMP_1)).addMBB(TBB);
|
||||
return 1;
|
||||
}
|
||||
|
||||
@ -3158,16 +3158,16 @@ X86InstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
|
||||
switch (CC) {
|
||||
case X86::COND_NP_OR_E:
|
||||
// Synthesize NP_OR_E with two branches.
|
||||
BuildMI(&MBB, DL, get(X86::JNP_4)).addMBB(TBB);
|
||||
BuildMI(&MBB, DL, get(X86::JNP_1)).addMBB(TBB);
|
||||
++Count;
|
||||
BuildMI(&MBB, DL, get(X86::JE_4)).addMBB(TBB);
|
||||
BuildMI(&MBB, DL, get(X86::JE_1)).addMBB(TBB);
|
||||
++Count;
|
||||
break;
|
||||
case X86::COND_NE_OR_P:
|
||||
// Synthesize NE_OR_P with two branches.
|
||||
BuildMI(&MBB, DL, get(X86::JNE_4)).addMBB(TBB);
|
||||
BuildMI(&MBB, DL, get(X86::JNE_1)).addMBB(TBB);
|
||||
++Count;
|
||||
BuildMI(&MBB, DL, get(X86::JP_4)).addMBB(TBB);
|
||||
BuildMI(&MBB, DL, get(X86::JP_1)).addMBB(TBB);
|
||||
++Count;
|
||||
break;
|
||||
default: {
|
||||
@ -3178,7 +3178,7 @@ X86InstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
|
||||
}
|
||||
if (FBB) {
|
||||
// Two-way Conditional branch. Insert the second branch.
|
||||
BuildMI(&MBB, DL, get(X86::JMP_4)).addMBB(FBB);
|
||||
BuildMI(&MBB, DL, get(X86::JMP_1)).addMBB(FBB);
|
||||
++Count;
|
||||
}
|
||||
return Count;
|
||||
@ -5344,26 +5344,26 @@ bool X86InstrInfo::shouldScheduleAdjacent(MachineInstr* First,
|
||||
switch(Second->getOpcode()) {
|
||||
default:
|
||||
return false;
|
||||
case X86::JE_4:
|
||||
case X86::JNE_4:
|
||||
case X86::JL_4:
|
||||
case X86::JLE_4:
|
||||
case X86::JG_4:
|
||||
case X86::JGE_4:
|
||||
case X86::JE_1:
|
||||
case X86::JNE_1:
|
||||
case X86::JL_1:
|
||||
case X86::JLE_1:
|
||||
case X86::JG_1:
|
||||
case X86::JGE_1:
|
||||
FuseKind = FuseInc;
|
||||
break;
|
||||
case X86::JB_4:
|
||||
case X86::JBE_4:
|
||||
case X86::JA_4:
|
||||
case X86::JAE_4:
|
||||
case X86::JB_1:
|
||||
case X86::JBE_1:
|
||||
case X86::JA_1:
|
||||
case X86::JAE_1:
|
||||
FuseKind = FuseCmp;
|
||||
break;
|
||||
case X86::JS_4:
|
||||
case X86::JNS_4:
|
||||
case X86::JP_4:
|
||||
case X86::JNP_4:
|
||||
case X86::JO_4:
|
||||
case X86::JNO_4:
|
||||
case X86::JS_1:
|
||||
case X86::JNS_1:
|
||||
case X86::JP_1:
|
||||
case X86::JNP_1:
|
||||
case X86::JO_1:
|
||||
case X86::JNO_1:
|
||||
FuseKind = FuseTest;
|
||||
break;
|
||||
}
|
||||
@ -5652,7 +5652,7 @@ void X86InstrInfo::getNoopForMachoTarget(MCInst &NopInst) const {
|
||||
// getUnconditionalBranch and getTrap.
|
||||
void X86InstrInfo::getUnconditionalBranch(
|
||||
MCInst &Branch, const MCSymbolRefExpr *BranchTarget) const {
|
||||
Branch.setOpcode(X86::JMP_4);
|
||||
Branch.setOpcode(X86::JMP_1);
|
||||
Branch.addOperand(MCOperand::CreateExpr(BranchTarget));
|
||||
}
|
||||
|
||||
|
@ -558,28 +558,6 @@ ReSimplify:
|
||||
case X86::ADD32ri8_DB: OutMI.setOpcode(X86::OR32ri8); goto ReSimplify;
|
||||
case X86::ADD64ri8_DB: OutMI.setOpcode(X86::OR64ri8); goto ReSimplify;
|
||||
|
||||
// The assembler backend wants to see branches in their small form and relax
|
||||
// them to their large form. The JIT can only handle the large form because
|
||||
// it does not do relaxation. For now, translate the large form to the
|
||||
// small one here.
|
||||
case X86::JMP_4: OutMI.setOpcode(X86::JMP_1); break;
|
||||
case X86::JO_4: OutMI.setOpcode(X86::JO_1); break;
|
||||
case X86::JNO_4: OutMI.setOpcode(X86::JNO_1); break;
|
||||
case X86::JB_4: OutMI.setOpcode(X86::JB_1); break;
|
||||
case X86::JAE_4: OutMI.setOpcode(X86::JAE_1); break;
|
||||
case X86::JE_4: OutMI.setOpcode(X86::JE_1); break;
|
||||
case X86::JNE_4: OutMI.setOpcode(X86::JNE_1); break;
|
||||
case X86::JBE_4: OutMI.setOpcode(X86::JBE_1); break;
|
||||
case X86::JA_4: OutMI.setOpcode(X86::JA_1); break;
|
||||
case X86::JS_4: OutMI.setOpcode(X86::JS_1); break;
|
||||
case X86::JNS_4: OutMI.setOpcode(X86::JNS_1); break;
|
||||
case X86::JP_4: OutMI.setOpcode(X86::JP_1); break;
|
||||
case X86::JNP_4: OutMI.setOpcode(X86::JNP_1); break;
|
||||
case X86::JL_4: OutMI.setOpcode(X86::JL_1); break;
|
||||
case X86::JGE_4: OutMI.setOpcode(X86::JGE_1); break;
|
||||
case X86::JLE_4: OutMI.setOpcode(X86::JLE_1); break;
|
||||
case X86::JG_4: OutMI.setOpcode(X86::JG_1); break;
|
||||
|
||||
// Atomic load and store require a separate pseudo-inst because Acquire
|
||||
// implies mayStore and Release implies mayLoad; fix these to regular MOV
|
||||
// instructions here
|
||||
|
Loading…
x
Reference in New Issue
Block a user