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X86: Don't generate 64-bit movd after cmpneqsd in 32-bit mode (PR19059)

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This fixes the bug where we would bitcast the 64-bit floating point result
of cmpneqsd to a 64-bit integer even on 32-bit targets.

Differential Revision: http://llvm-reviews.chandlerc.com/D3009

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203581 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Hans Wennborg 2014-03-11 15:49:24 +00:00
parent 4f45d04c6f
commit 1332459dbb
2 changed files with 46 additions and 6 deletions
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24
lib/Target/X86/X86ISelLowering.cpp
View File

@ -18044,7 +18044,6 @@ static SDValue CMPEQCombine(SDNode *N, SelectionDAG &DAG,
if ((cc0 == X86::COND_E && cc1 == X86::COND_NP) ||
(cc0 == X86::COND_NE && cc1 == X86::COND_P)) {
bool is64BitFP = (CMP00.getValueType() == MVT::f64);
// FIXME: need symbolic constants for these magic numbers.
// See X86ATTInstPrinter.cpp:printSSECC().
unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4;
@ -18059,9 +18058,26 @@ static SDValue CMPEQCombine(SDNode *N, SelectionDAG &DAG,
SDValue OnesOrZeroesF = DAG.getNode(X86ISD::FSETCC, DL,
CMP00.getValueType(), CMP00, CMP01,
DAG.getConstant(x86cc, MVT::i8));
MVT IntVT = (is64BitFP ? MVT::i64 : MVT::i32);
SDValue OnesOrZeroesI = DAG.getNode(ISD::BITCAST, DL, IntVT,
OnesOrZeroesF);
bool is64BitFP = (CMP00.getValueType() == MVT::f64);
MVT IntVT = is64BitFP ? MVT::i64 : MVT::i32;
if (is64BitFP && !Subtarget->is64Bit()) {
// On a 32-bit target, we cannot bitcast the 64-bit float to a
// 64-bit integer, since that's not a legal type. Since
// OnesOrZeroesF is all ones of all zeroes, we don't need all the
// bits, but can do this little dance to extract the lowest 32 bits
// and work with those going forward.
SDValue Vector64 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f64,
OnesOrZeroesF);
SDValue Vector32 = DAG.getNode(ISD::BITCAST, DL, MVT::v4f32,
Vector64);
OnesOrZeroesF = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32,
Vector32, DAG.getIntPtrConstant(0));
IntVT = MVT::i32;
}
SDValue OnesOrZeroesI = DAG.getNode(ISD::BITCAST, DL, IntVT, OnesOrZeroesF);
SDValue ANDed = DAG.getNode(ISD::AND, DL, IntVT, OnesOrZeroesI,
DAG.getConstant(1, IntVT));
SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8, ANDed);

28
test/CodeGen/X86/isint.ll
View File

@ -1,6 +1,11 @@
; RUN: llc < %s -march=x86 -mattr=+sse2 -mcpu=penryn| FileCheck %s
; RUN: llc < %s -mtriple=x86_64-pc-unknown -mattr=+sse2 -mcpu=penryn | FileCheck %s
; RUN: llc < %s -mtriple=i686-pc-unknown -mattr=+sse2 -mcpu=penryn | FileCheck %s
; PR19059
; RUN: llc < %s -mtriple=i686-pc-unknown -mattr=+sse2 -mcpu=penryn | FileCheck -check-prefix=CHECK32 %s
define i32 @isint_return(double %d) nounwind {
; CHECK-LABEL: isint_return:
; CHECK-NOT: xor
; CHECK: cvt
%i = fptosi double %d to i32
@ -8,8 +13,26 @@ define i32 @isint_return(double %d) nounwind {
%e = sitofp i32 %i to double
; CHECK: cmpeqsd
%c = fcmp oeq double %d, %e
; CHECK32-NOT: movd {{.*}}, %r{{.*}}
; CHECK32-NOT: andq
; CHECK-NEXT: movd
; CHECK-NEXT: andq
; CHECK-NEXT: andl
%z = zext i1 %c to i32
ret i32 %z
}
define i32 @isint_float_return(float %f) nounwind {
; CHECK-LABEL: isint_float_return:
; CHECK-NOT: xor
; CHECK: cvt
%i = fptosi float %f to i32
; CHECK-NEXT: cvt
%g = sitofp i32 %i to float
; CHECK: cmpeqss
%c = fcmp oeq float %f, %g
; CHECK-NOT: movd {{.*}}, %r{{.*}}
; CHECK-NEXT: movd
; CHECK-NEXT: andl
%z = zext i1 %c to i32
ret i32 %z
}
@ -17,6 +40,7 @@ define i32 @isint_return(double %d) nounwind {
declare void @foo()
define void @isint_branch(double %d) nounwind {
; CHECK-LABEL: isint_branch:
; CHECK: cvt
%i = fptosi double %d to i32
; CHECK-NEXT: cvt