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Code Issues Projects Releases Wiki Activity

Rename the redundant MachineOperand::getOperandType() to MachineOperand::getType()

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4331 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2002-10-28 04:45:29 +00:00
parent 6d6c3f8618
commit 133f079c8c
12 changed files with 101 additions and 104 deletions
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4
include/llvm/CodeGen/MachineInstr.h
View File

@ -101,7 +101,7 @@ public:
// Accessor methods. Caller is responsible for checking the
// operand type before invoking the corresponding accessor.
//
MachineOperandType getOperandType() const { return opType; }
MachineOperandType getType() const { return opType; }
inline Value* getVRegValue () const {
assert(opType == MO_VirtualRegister || opType == MO_CCRegister ||
@ -248,7 +248,7 @@ public:
}
MachineOperand::MachineOperandType getOperandType(unsigned i) const {
return getOperand(i).getOperandType();
return getOperand(i).getType();
}
bool operandIsDefined(unsigned i) const {

41
lib/CodeGen/InstrSched/SchedGraph.cpp
View File

@ -623,31 +623,30 @@ SchedGraph::addEdgesForValue(SchedGraphNode* refNode,
void
SchedGraph::addEdgesForInstruction(const MachineInstr& minstr,
SchedGraph::addEdgesForInstruction(const MachineInstr& MI,
const ValueToDefVecMap& valueToDefVecMap,
const TargetMachine& target)
{
SchedGraphNode* node = this->getGraphNodeForInstr(&minstr);
SchedGraphNode* node = getGraphNodeForInstr(&MI);
if (node == NULL)
return;
// Add edges for all operands of the machine instruction.
//
for (unsigned i=0, numOps=minstr.getNumOperands(); i < numOps; i++)
for (unsigned i = 0, numOps = MI.getNumOperands(); i != numOps; ++i)
{
const MachineOperand& mop = minstr.getOperand(i);
switch(mop.getOperandType())
switch (MI.getOperandType(i))
{
case MachineOperand::MO_VirtualRegister:
case MachineOperand::MO_CCRegister:
if (const Instruction* srcI =
dyn_cast_or_null<Instruction>(mop.getVRegValue()))
dyn_cast_or_null<Instruction>(MI.getOperand(i).getVRegValue()))
{
ValueToDefVecMap::const_iterator I = valueToDefVecMap.find(srcI);
if (I != valueToDefVecMap.end())
addEdgesForValue(node, (*I).second, mop.getVRegValue(),
minstr.operandIsDefined(i),
minstr.operandIsDefinedAndUsed(i), target);
addEdgesForValue(node, I->second, srcI,
MI.operandIsDefined(i),
MI.operandIsDefinedAndUsed(i), target);
}
break;
@ -669,17 +668,17 @@ SchedGraph::addEdgesForInstruction(const MachineInstr& minstr,
// Examples include function arguments to a Call instructions or the return
// value of a Ret instruction.
//
for (unsigned i=0, N=minstr.getNumImplicitRefs(); i < N; ++i)
if (! minstr.implicitRefIsDefined(i) ||
minstr.implicitRefIsDefinedAndUsed(i))
if (const Instruction* srcI =
dyn_cast_or_null<Instruction>(minstr.getImplicitRef(i)))
for (unsigned i=0, N=MI.getNumImplicitRefs(); i < N; ++i)
if (! MI.implicitRefIsDefined(i) ||
MI.implicitRefIsDefinedAndUsed(i))
if (const Instruction *srcI =
dyn_cast_or_null<Instruction>(MI.getImplicitRef(i)))
{
ValueToDefVecMap::const_iterator I = valueToDefVecMap.find(srcI);
if (I != valueToDefVecMap.end())
addEdgesForValue(node, (*I).second, minstr.getImplicitRef(i),
minstr.implicitRefIsDefined(i),
minstr.implicitRefIsDefinedAndUsed(i), target);
addEdgesForValue(node, I->second, srcI,
MI.implicitRefIsDefined(i),
MI.implicitRefIsDefinedAndUsed(i), target);
}
}
@ -700,14 +699,14 @@ SchedGraph::findDefUseInfoAtInstr(const TargetMachine& target,
// Collect the register references and value defs. for explicit operands
//
const MachineInstr& minstr = * node->getMachineInstr();
const MachineInstr& minstr = *node->getMachineInstr();
for (int i=0, numOps = (int) minstr.getNumOperands(); i < numOps; i++)
{
const MachineOperand& mop = minstr.getOperand(i);
// if this references a register other than the hardwired
// "zero" register, record the reference.
if (mop.getOperandType() == MachineOperand::MO_MachineRegister)
if (mop.getType() == MachineOperand::MO_MachineRegister)
{
int regNum = mop.getMachineRegNum();
if (regNum != target.getRegInfo().getZeroRegNum())
@ -721,8 +720,8 @@ SchedGraph::findDefUseInfoAtInstr(const TargetMachine& target,
continue;
// We must be defining a value.
assert((mop.getOperandType() == MachineOperand::MO_VirtualRegister ||
mop.getOperandType() == MachineOperand::MO_CCRegister)
assert((mop.getType() == MachineOperand::MO_VirtualRegister ||
mop.getType() == MachineOperand::MO_CCRegister)
&& "Do not expect any other kind of operand to be defined!");
const Instruction* defInstr = cast<Instruction>(mop.getVRegValue());

16
lib/CodeGen/InstrSelection/InstrSelectionSupport.cpp
View File

@ -483,9 +483,9 @@ FixConstantOperandsForInstr(Instruction* vmInstr,
// Skip the result position, preallocated machine registers, or operands
// that cannot be constants (CC regs or PC-relative displacements)
if (instrDesc.resultPos == (int) op ||
mop.getOperandType() == MachineOperand::MO_MachineRegister ||
mop.getOperandType() == MachineOperand::MO_CCRegister ||
mop.getOperandType() == MachineOperand::MO_PCRelativeDisp)
mop.getType() == MachineOperand::MO_MachineRegister ||
mop.getType() == MachineOperand::MO_CCRegister ||
mop.getType() == MachineOperand::MO_PCRelativeDisp)
continue;
bool constantThatMustBeLoaded = false;
@ -496,7 +496,7 @@ FixConstantOperandsForInstr(Instruction* vmInstr,
MachineOperand::MO_VirtualRegister;
// Operand may be a virtual register or a compile-time constant
if (mop.getOperandType() == MachineOperand::MO_VirtualRegister)
if (mop.getType() == MachineOperand::MO_VirtualRegister)
{
assert(mop.getVRegValue() != NULL);
opValue = mop.getVRegValue();
@ -510,10 +510,10 @@ FixConstantOperandsForInstr(Instruction* vmInstr,
}
else
{
assert(mop.getOperandType() == MachineOperand::MO_SignExtendedImmed ||
mop.getOperandType() == MachineOperand::MO_UnextendedImmed);
assert(mop.getType() == MachineOperand::MO_SignExtendedImmed ||
mop.getType() == MachineOperand::MO_UnextendedImmed);
bool isSigned = (mop.getOperandType() ==
bool isSigned = (mop.getType() ==
MachineOperand::MO_SignExtendedImmed);
// Bit-selection flags indicate an instruction that is extracting
@ -526,7 +526,7 @@ FixConstantOperandsForInstr(Instruction* vmInstr,
opCode, target, (immedPos == (int)op),
machineRegNum, immedValue);
if (opType == mop.getOperandType())
if (opType == mop.getType())
continue; // no change: this is the most common case
if (opType == MachineOperand::MO_VirtualRegister)

12
lib/CodeGen/RegAlloc/LiveRangeInfo.cpp
View File

@ -110,7 +110,7 @@ LiveRangeInfo::createOrAddToLiveRange(const Value* Def, bool isCC /* = false*/)
// check if the LR is already there (because of multiple defs)
if (!DefRange) {
DefRange = this->createNewLiveRange(Def, isCC);
DefRange = createNewLiveRange(Def, isCC);
} else { // live range already exists
DefRange->insert(Def); // add the operand to the range
LiveRangeMap[Def] = DefRange; // make operand point to merged set
@ -134,7 +134,7 @@ void LiveRangeInfo::constructLiveRanges() {
// first find the live ranges for all incoming args of the function since
// those LRs start from the start of the function
for (Function::const_aiterator AI = Meth->abegin(); AI != Meth->aend(); ++AI)
this->createNewLiveRange(AI, /*isCC*/ false);
createNewLiveRange(AI, /*isCC*/ false);
// Now suggest hardware registers for these function args
MRI.suggestRegs4MethodArgs(Meth, *this);
@ -160,7 +160,7 @@ void LiveRangeInfo::constructLiveRanges() {
//
if(TM.getInstrInfo().isReturn(MInst->getOpCode()) ||
TM.getInstrInfo().isCall(MInst->getOpCode()))
CallRetInstrList.push_back( MInst );
CallRetInstrList.push_back(MInst);
// iterate over explicit MI operands and create a new LR
// for each operand that is defined by the instruction
@ -168,9 +168,9 @@ void LiveRangeInfo::constructLiveRanges() {
OpE = MInst->end(); OpI != OpE; ++OpI)
if (OpI.isDef()) {
const Value *Def = *OpI;
bool isCC = (OpI.getMachineOperand().getOperandType()
bool isCC = (OpI.getMachineOperand().getType()
== MachineOperand::MO_CCRegister);
this->createOrAddToLiveRange(Def, isCC);
createOrAddToLiveRange(Def, isCC);
}
// iterate over implicit MI operands and create a new LR
@ -178,7 +178,7 @@ void LiveRangeInfo::constructLiveRanges() {
for (unsigned i = 0; i < MInst->getNumImplicitRefs(); ++i)
if (MInst->implicitRefIsDefined(i)) {
const Value *Def = MInst->getImplicitRef(i);
this->createOrAddToLiveRange(Def, /*isCC*/ false);
createOrAddToLiveRange(Def, /*isCC*/ false);
}
} // for all machine instructions in the BB

22
lib/CodeGen/RegAlloc/PhyRegAlloc.cpp
View File

@ -539,8 +539,8 @@ void PhyRegAlloc::updateMachineCode()
for (unsigned OpNum=0; OpNum < MInst->getNumOperands(); ++OpNum)
{
MachineOperand& Op = MInst->getOperand(OpNum);
if (Op.getOperandType() == MachineOperand::MO_VirtualRegister ||
Op.getOperandType() == MachineOperand::MO_CCRegister)
if (Op.getType() == MachineOperand::MO_VirtualRegister ||
Op.getType() == MachineOperand::MO_CCRegister)
{
const Value *const Val = Op.getVRegValue();
@ -750,7 +750,7 @@ int PhyRegAlloc::getUsableUniRegAtMI(const int RegType,
std::vector<MachineInstr*>& MIBef,
std::vector<MachineInstr*>& MIAft) {
RegClass* RC = this->getRegClassByID(MRI.getRegClassIDOfRegType(RegType));
RegClass* RC = getRegClassByID(MRI.getRegClassIDOfRegType(RegType));
int RegU = getUnusedUniRegAtMI(RC, MInst, LVSetBef);
@ -766,8 +766,8 @@ int PhyRegAlloc::getUsableUniRegAtMI(const int RegType,
int scratchRegType = -1;
if (MRI.regTypeNeedsScratchReg(RegType, scratchRegType))
{
int scratchReg = this->getUsableUniRegAtMI(scratchRegType, LVSetBef,
MInst, MIBef, MIAft);
int scratchReg = getUsableUniRegAtMI(scratchRegType, LVSetBef,
MInst, MIBef, MIAft);
assert(scratchReg != MRI.getInvalidRegNum());
// We may as well hold the value in the scratch register instead
@ -893,8 +893,8 @@ void PhyRegAlloc::setRelRegsUsedByThisInst(RegClass *RC,
{
const MachineOperand& Op = MInst->getOperand(OpNum);
if (Op.getOperandType() == MachineOperand::MO_VirtualRegister ||
Op.getOperandType() == MachineOperand::MO_CCRegister)
if (MInst->getOperandType(OpNum) == MachineOperand::MO_VirtualRegister ||
MInst->getOperandType(OpNum) == MachineOperand::MO_CCRegister)
if (const Value* Val = Op.getVRegValue())
if (MRI.getRegClassIDOfValue(Val) == RC->getID())
if (Op.getAllocatedRegNum() == -1)
@ -971,9 +971,9 @@ void PhyRegAlloc::printMachineCode()
for (unsigned OpNum=0; OpNum < MInst->getNumOperands(); ++OpNum) {
MachineOperand& Op = MInst->getOperand(OpNum);
if (Op.getOperandType() == MachineOperand::MO_VirtualRegister ||
Op.getOperandType() == MachineOperand::MO_CCRegister /*||
Op.getOperandType() == MachineOperand::MO_PCRelativeDisp*/ ) {
if (Op.getType() == MachineOperand::MO_VirtualRegister ||
Op.getType() == MachineOperand::MO_CCRegister /*||
Op.getType() == MachineOperand::MO_PCRelativeDisp*/ ) {
const Value *const Val = Op.getVRegValue () ;
// ****this code is temporary till NULL Values are fixed
@ -1005,7 +1005,7 @@ void PhyRegAlloc::printMachineCode()
}
}
else if (Op.getOperandType() == MachineOperand::MO_MachineRegister) {
else if (Op.getType() == MachineOperand::MO_MachineRegister) {
cerr << "\t" << "%" << MRI.getUnifiedRegName(Op.getMachineRegNum());
}

41
lib/Target/SparcV9/InstrSched/SchedGraph.cpp
View File

@ -623,31 +623,30 @@ SchedGraph::addEdgesForValue(SchedGraphNode* refNode,
void
SchedGraph::addEdgesForInstruction(const MachineInstr& minstr,
SchedGraph::addEdgesForInstruction(const MachineInstr& MI,
const ValueToDefVecMap& valueToDefVecMap,
const TargetMachine& target)
{
SchedGraphNode* node = this->getGraphNodeForInstr(&minstr);
SchedGraphNode* node = getGraphNodeForInstr(&MI);
if (node == NULL)
return;
// Add edges for all operands of the machine instruction.
//
for (unsigned i=0, numOps=minstr.getNumOperands(); i < numOps; i++)
for (unsigned i = 0, numOps = MI.getNumOperands(); i != numOps; ++i)
{
const MachineOperand& mop = minstr.getOperand(i);
switch(mop.getOperandType())
switch (MI.getOperandType(i))
{
case MachineOperand::MO_VirtualRegister:
case MachineOperand::MO_CCRegister:
if (const Instruction* srcI =
dyn_cast_or_null<Instruction>(mop.getVRegValue()))
dyn_cast_or_null<Instruction>(MI.getOperand(i).getVRegValue()))
{
ValueToDefVecMap::const_iterator I = valueToDefVecMap.find(srcI);
if (I != valueToDefVecMap.end())
addEdgesForValue(node, (*I).second, mop.getVRegValue(),
minstr.operandIsDefined(i),
minstr.operandIsDefinedAndUsed(i), target);
addEdgesForValue(node, I->second, srcI,
MI.operandIsDefined(i),
MI.operandIsDefinedAndUsed(i), target);
}
break;
@ -669,17 +668,17 @@ SchedGraph::addEdgesForInstruction(const MachineInstr& minstr,
// Examples include function arguments to a Call instructions or the return
// value of a Ret instruction.
//
for (unsigned i=0, N=minstr.getNumImplicitRefs(); i < N; ++i)
if (! minstr.implicitRefIsDefined(i) ||
minstr.implicitRefIsDefinedAndUsed(i))
if (const Instruction* srcI =
dyn_cast_or_null<Instruction>(minstr.getImplicitRef(i)))
for (unsigned i=0, N=MI.getNumImplicitRefs(); i < N; ++i)
if (! MI.implicitRefIsDefined(i) ||
MI.implicitRefIsDefinedAndUsed(i))
if (const Instruction *srcI =
dyn_cast_or_null<Instruction>(MI.getImplicitRef(i)))
{
ValueToDefVecMap::const_iterator I = valueToDefVecMap.find(srcI);
if (I != valueToDefVecMap.end())
addEdgesForValue(node, (*I).second, minstr.getImplicitRef(i),
minstr.implicitRefIsDefined(i),
minstr.implicitRefIsDefinedAndUsed(i), target);
addEdgesForValue(node, I->second, srcI,
MI.implicitRefIsDefined(i),
MI.implicitRefIsDefinedAndUsed(i), target);
}
}
@ -700,14 +699,14 @@ SchedGraph::findDefUseInfoAtInstr(const TargetMachine& target,
// Collect the register references and value defs. for explicit operands
//
const MachineInstr& minstr = * node->getMachineInstr();
const MachineInstr& minstr = *node->getMachineInstr();
for (int i=0, numOps = (int) minstr.getNumOperands(); i < numOps; i++)
{
const MachineOperand& mop = minstr.getOperand(i);
// if this references a register other than the hardwired
// "zero" register, record the reference.
if (mop.getOperandType() == MachineOperand::MO_MachineRegister)
if (mop.getType() == MachineOperand::MO_MachineRegister)
{
int regNum = mop.getMachineRegNum();
if (regNum != target.getRegInfo().getZeroRegNum())
@ -721,8 +720,8 @@ SchedGraph::findDefUseInfoAtInstr(const TargetMachine& target,
continue;
// We must be defining a value.
assert((mop.getOperandType() == MachineOperand::MO_VirtualRegister ||
mop.getOperandType() == MachineOperand::MO_CCRegister)
assert((mop.getType() == MachineOperand::MO_VirtualRegister ||
mop.getType() == MachineOperand::MO_CCRegister)
&& "Do not expect any other kind of operand to be defined!");
const Instruction* defInstr = cast<Instruction>(mop.getVRegValue());

16
lib/Target/SparcV9/InstrSelection/InstrSelectionSupport.cpp
View File

@ -483,9 +483,9 @@ FixConstantOperandsForInstr(Instruction* vmInstr,
// Skip the result position, preallocated machine registers, or operands
// that cannot be constants (CC regs or PC-relative displacements)
if (instrDesc.resultPos == (int) op ||
mop.getOperandType() == MachineOperand::MO_MachineRegister ||
mop.getOperandType() == MachineOperand::MO_CCRegister ||
mop.getOperandType() == MachineOperand::MO_PCRelativeDisp)
mop.getType() == MachineOperand::MO_MachineRegister ||
mop.getType() == MachineOperand::MO_CCRegister ||
mop.getType() == MachineOperand::MO_PCRelativeDisp)
continue;
bool constantThatMustBeLoaded = false;
@ -496,7 +496,7 @@ FixConstantOperandsForInstr(Instruction* vmInstr,
MachineOperand::MO_VirtualRegister;
// Operand may be a virtual register or a compile-time constant
if (mop.getOperandType() == MachineOperand::MO_VirtualRegister)
if (mop.getType() == MachineOperand::MO_VirtualRegister)
{
assert(mop.getVRegValue() != NULL);
opValue = mop.getVRegValue();
@ -510,10 +510,10 @@ FixConstantOperandsForInstr(Instruction* vmInstr,
}
else
{
assert(mop.getOperandType() == MachineOperand::MO_SignExtendedImmed ||
mop.getOperandType() == MachineOperand::MO_UnextendedImmed);
assert(mop.getType() == MachineOperand::MO_SignExtendedImmed ||
mop.getType() == MachineOperand::MO_UnextendedImmed);
bool isSigned = (mop.getOperandType() ==
bool isSigned = (mop.getType() ==
MachineOperand::MO_SignExtendedImmed);
// Bit-selection flags indicate an instruction that is extracting
@ -526,7 +526,7 @@ FixConstantOperandsForInstr(Instruction* vmInstr,
opCode, target, (immedPos == (int)op),
machineRegNum, immedValue);
if (opType == mop.getOperandType())
if (opType == mop.getType())
continue; // no change: this is the most common case
if (opType == MachineOperand::MO_VirtualRegister)

12
lib/Target/SparcV9/RegAlloc/LiveRangeInfo.cpp
View File

@ -110,7 +110,7 @@ LiveRangeInfo::createOrAddToLiveRange(const Value* Def, bool isCC /* = false*/)
// check if the LR is already there (because of multiple defs)
if (!DefRange) {
DefRange = this->createNewLiveRange(Def, isCC);
DefRange = createNewLiveRange(Def, isCC);
} else { // live range already exists
DefRange->insert(Def); // add the operand to the range
LiveRangeMap[Def] = DefRange; // make operand point to merged set
@ -134,7 +134,7 @@ void LiveRangeInfo::constructLiveRanges() {
// first find the live ranges for all incoming args of the function since
// those LRs start from the start of the function
for (Function::const_aiterator AI = Meth->abegin(); AI != Meth->aend(); ++AI)
this->createNewLiveRange(AI, /*isCC*/ false);
createNewLiveRange(AI, /*isCC*/ false);
// Now suggest hardware registers for these function args
MRI.suggestRegs4MethodArgs(Meth, *this);
@ -160,7 +160,7 @@ void LiveRangeInfo::constructLiveRanges() {
//
if(TM.getInstrInfo().isReturn(MInst->getOpCode()) ||
TM.getInstrInfo().isCall(MInst->getOpCode()))
CallRetInstrList.push_back( MInst );
CallRetInstrList.push_back(MInst);
// iterate over explicit MI operands and create a new LR
// for each operand that is defined by the instruction
@ -168,9 +168,9 @@ void LiveRangeInfo::constructLiveRanges() {
OpE = MInst->end(); OpI != OpE; ++OpI)
if (OpI.isDef()) {
const Value *Def = *OpI;
bool isCC = (OpI.getMachineOperand().getOperandType()
bool isCC = (OpI.getMachineOperand().getType()
== MachineOperand::MO_CCRegister);
this->createOrAddToLiveRange(Def, isCC);
createOrAddToLiveRange(Def, isCC);
}
// iterate over implicit MI operands and create a new LR
@ -178,7 +178,7 @@ void LiveRangeInfo::constructLiveRanges() {
for (unsigned i = 0; i < MInst->getNumImplicitRefs(); ++i)
if (MInst->implicitRefIsDefined(i)) {
const Value *Def = MInst->getImplicitRef(i);
this->createOrAddToLiveRange(Def, /*isCC*/ false);
createOrAddToLiveRange(Def, /*isCC*/ false);
}
} // for all machine instructions in the BB

22
lib/Target/SparcV9/RegAlloc/PhyRegAlloc.cpp
View File

@ -539,8 +539,8 @@ void PhyRegAlloc::updateMachineCode()
for (unsigned OpNum=0; OpNum < MInst->getNumOperands(); ++OpNum)
{
MachineOperand& Op = MInst->getOperand(OpNum);
if (Op.getOperandType() == MachineOperand::MO_VirtualRegister ||
Op.getOperandType() == MachineOperand::MO_CCRegister)
if (Op.getType() == MachineOperand::MO_VirtualRegister ||
Op.getType() == MachineOperand::MO_CCRegister)
{
const Value *const Val = Op.getVRegValue();
@ -750,7 +750,7 @@ int PhyRegAlloc::getUsableUniRegAtMI(const int RegType,
std::vector<MachineInstr*>& MIBef,
std::vector<MachineInstr*>& MIAft) {
RegClass* RC = this->getRegClassByID(MRI.getRegClassIDOfRegType(RegType));
RegClass* RC = getRegClassByID(MRI.getRegClassIDOfRegType(RegType));
int RegU = getUnusedUniRegAtMI(RC, MInst, LVSetBef);
@ -766,8 +766,8 @@ int PhyRegAlloc::getUsableUniRegAtMI(const int RegType,
int scratchRegType = -1;
if (MRI.regTypeNeedsScratchReg(RegType, scratchRegType))
{
int scratchReg = this->getUsableUniRegAtMI(scratchRegType, LVSetBef,
MInst, MIBef, MIAft);
int scratchReg = getUsableUniRegAtMI(scratchRegType, LVSetBef,
MInst, MIBef, MIAft);
assert(scratchReg != MRI.getInvalidRegNum());
// We may as well hold the value in the scratch register instead
@ -893,8 +893,8 @@ void PhyRegAlloc::setRelRegsUsedByThisInst(RegClass *RC,
{
const MachineOperand& Op = MInst->getOperand(OpNum);
if (Op.getOperandType() == MachineOperand::MO_VirtualRegister ||
Op.getOperandType() == MachineOperand::MO_CCRegister)
if (MInst->getOperandType(OpNum) == MachineOperand::MO_VirtualRegister ||
MInst->getOperandType(OpNum) == MachineOperand::MO_CCRegister)
if (const Value* Val = Op.getVRegValue())
if (MRI.getRegClassIDOfValue(Val) == RC->getID())
if (Op.getAllocatedRegNum() == -1)
@ -971,9 +971,9 @@ void PhyRegAlloc::printMachineCode()
for (unsigned OpNum=0; OpNum < MInst->getNumOperands(); ++OpNum) {
MachineOperand& Op = MInst->getOperand(OpNum);
if (Op.getOperandType() == MachineOperand::MO_VirtualRegister ||
Op.getOperandType() == MachineOperand::MO_CCRegister /*||
Op.getOperandType() == MachineOperand::MO_PCRelativeDisp*/ ) {
if (Op.getType() == MachineOperand::MO_VirtualRegister ||
Op.getType() == MachineOperand::MO_CCRegister /*||
Op.getType() == MachineOperand::MO_PCRelativeDisp*/ ) {
const Value *const Val = Op.getVRegValue () ;
// ****this code is temporary till NULL Values are fixed
@ -1005,7 +1005,7 @@ void PhyRegAlloc::printMachineCode()
}
}
else if (Op.getOperandType() == MachineOperand::MO_MachineRegister) {
else if (Op.getType() == MachineOperand::MO_MachineRegister) {
cerr << "\t" << "%" << MRI.getUnifiedRegName(Op.getMachineRegNum());
}

2
lib/Target/SparcV9/SparcV9AsmPrinter.cpp
View File

@ -382,7 +382,7 @@ SparcFunctionAsmPrinter::printOneOperand(const MachineOperand &mop)
else
needBitsFlag = false;
switch (mop.getOperandType())
switch (mop.getType())
{
case MachineOperand::MO_VirtualRegister:
case MachineOperand::MO_CCRegister:

2
lib/Target/SparcV9/SparcV9InstrSelection.cpp
View File

@ -1106,7 +1106,7 @@ ForwardOperand(InstructionNode* treeNode,
for (unsigned i=0, numOps=minstr->getNumOperands(); i < numOps; ++i)
{
const MachineOperand& mop = minstr->getOperand(i);
if (mop.getOperandType() == MachineOperand::MO_VirtualRegister &&
if (mop.getType() == MachineOperand::MO_VirtualRegister &&
mop.getVRegValue() == unusedOp)
minstr->SetMachineOperandVal(i,
MachineOperand::MO_VirtualRegister, fwdOp);

15
lib/Target/SparcV9/SparcV9RegInfo.cpp
View File

@ -1599,11 +1599,10 @@ void UltraSparcRegInfo::OrderAddedInstrns(std::vector<MachineInstr*> &UnordVec,
// last operand is the def (unless for a store which has no def reg)
MachineOperand& DefOp = DefInst->getOperand(DefInst->getNumOperands()-1);
if( DefOp.opIsDef() &&
DefOp.getOperandType() == MachineOperand::MO_MachineRegister) {
if (DefOp.opIsDef() &&
DefOp.getType() == MachineOperand::MO_MachineRegister) {
// If the operand in DefInst is a def ...
bool DefEqUse = false;
std::vector<MachineInstr *>::iterator UseIt = DefIt;
@ -1617,8 +1616,8 @@ void UltraSparcRegInfo::OrderAddedInstrns(std::vector<MachineInstr*> &UnordVec,
// for each inst (UseInst) that is below the DefInst do ...
MachineOperand& UseOp = UseInst->getOperand(0);
if( ! UseOp.opIsDef() &&
UseOp.getOperandType() == MachineOperand::MO_MachineRegister) {
if (!UseOp.opIsDef() &&
UseOp.getType() == MachineOperand::MO_MachineRegister) {
// if use is a register ...
@ -1678,8 +1677,8 @@ void UltraSparcRegInfo::moveInst2OrdVec(std::vector<MachineInstr *> &OrdVec,
PhyRegAlloc &PRA) const {
MachineOperand& UseOp = UnordInst->getOperand(0);
if( ! UseOp.opIsDef() &&
UseOp.getOperandType() == MachineOperand::MO_MachineRegister) {
if (!UseOp.opIsDef() &&
UseOp.getType() == MachineOperand::MO_MachineRegister) {
// for the use of UnordInst, see whether there is a defining instr
// before in the OrdVec
@ -1695,7 +1694,7 @@ void UltraSparcRegInfo::moveInst2OrdVec(std::vector<MachineInstr *> &OrdVec,
OrdInst->getOperand(OrdInst->getNumOperands()-1);
if( DefOp.opIsDef() &&
DefOp.getOperandType() == MachineOperand::MO_MachineRegister) {
DefOp.getType() == MachineOperand::MO_MachineRegister) {
//cerr << "\nDefining Ord Inst: " << *OrdInst;