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fix a bug in my previous checkin

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25244 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2006-01-12 07:38:04 +00:00
parent 72878a463b
commit 138d322e96
2 changed files with 6 additions and 4 deletions
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5
lib/Target/Sparc/SparcISelDAGToDAG.cpp
View File

@ -165,6 +165,7 @@ SparcV8TargetLowering::SparcV8TargetLowering(TargetMachine &TM)
const char *SparcV8TargetLowering::getTargetNodeName(unsigned Opcode) const {
switch (Opcode) {
default: return 0;
case V8ISD::CMPICC: return "V8ISD::CMPICC";
case V8ISD::CMPFCC: return "V8ISD::CMPFCC";
case V8ISD::BRICC: return "V8ISD::BRICC";
@ -661,7 +662,7 @@ LowerOperation(SDOperand Op, SelectionDAG &DAG) {
std::vector<SDOperand> Ops;
Ops.push_back(LHS);
Ops.push_back(RHS);
SDOperand Cond = DAG.getNode(V8ISD::CMPICC, VTs, Ops);
SDOperand Cond = DAG.getNode(V8ISD::CMPICC, VTs, Ops).getValue(1);
return DAG.getNode(V8ISD::BRICC, MVT::Other, Chain, Dest, CC, Cond);
} else {
std::vector<MVT::ValueType> VTs;
@ -670,7 +671,7 @@ LowerOperation(SDOperand Op, SelectionDAG &DAG) {
std::vector<SDOperand> Ops;
Ops.push_back(LHS);
Ops.push_back(RHS);
SDOperand Cond = DAG.getNode(V8ISD::CMPFCC, VTs, Ops);
SDOperand Cond = DAG.getNode(V8ISD::CMPFCC, VTs, Ops).getValue(1);
return DAG.getNode(V8ISD::BRFCC, MVT::Other, Chain, Dest, CC, Cond);
}
}

5
lib/Target/SparcV8/SparcV8ISelDAGToDAG.cpp
View File

@ -165,6 +165,7 @@ SparcV8TargetLowering::SparcV8TargetLowering(TargetMachine &TM)
const char *SparcV8TargetLowering::getTargetNodeName(unsigned Opcode) const {
switch (Opcode) {
default: return 0;
case V8ISD::CMPICC: return "V8ISD::CMPICC";
case V8ISD::CMPFCC: return "V8ISD::CMPFCC";
case V8ISD::BRICC: return "V8ISD::BRICC";
@ -661,7 +662,7 @@ LowerOperation(SDOperand Op, SelectionDAG &DAG) {
std::vector<SDOperand> Ops;
Ops.push_back(LHS);
Ops.push_back(RHS);
SDOperand Cond = DAG.getNode(V8ISD::CMPICC, VTs, Ops);
SDOperand Cond = DAG.getNode(V8ISD::CMPICC, VTs, Ops).getValue(1);
return DAG.getNode(V8ISD::BRICC, MVT::Other, Chain, Dest, CC, Cond);
} else {
std::vector<MVT::ValueType> VTs;
@ -670,7 +671,7 @@ LowerOperation(SDOperand Op, SelectionDAG &DAG) {
std::vector<SDOperand> Ops;
Ops.push_back(LHS);
Ops.push_back(RHS);
SDOperand Cond = DAG.getNode(V8ISD::CMPFCC, VTs, Ops);
SDOperand Cond = DAG.getNode(V8ISD::CMPFCC, VTs, Ops).getValue(1);
return DAG.getNode(V8ISD::BRFCC, MVT::Other, Chain, Dest, CC, Cond);
}
}