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Use the new TRI->getLargestLegalSuperClass hook to constrain register class inflation.

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This has two effects: 1. We never inflate to a larger register class than what
the sub-target can handle. 2. Completely unconstrained virtual registers get the
largest possible register class.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130229 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jakob Stoklund Olesen
2011-04-26 18:52:36 +00:00
parent c9e5015dec
commit 1394e6d925
2 changed files with 35 additions and 56 deletions
Download Patch File Download Diff File Expand all files Collapse all files

10
include/llvm/CodeGen/CalcSpillWeights.h
View File

@@ -40,14 +40,14 @@ namespace llvm {
/// VirtRegAuxInfo - Calculate auxiliary information for a virtual /// VirtRegAuxInfo - Calculate auxiliary information for a virtual
/// register such as its spill weight and allocation hint. /// register such as its spill weight and allocation hint.
class VirtRegAuxInfo { class VirtRegAuxInfo {
MachineFunction &mf_; MachineFunction &MF;
LiveIntervals &lis_; LiveIntervals &LIS;
const MachineLoopInfo &loops_; const MachineLoopInfo &Loops;
DenseMap<unsigned, float> hint_; DenseMap<unsigned, float> Hint;
public: public:
VirtRegAuxInfo(MachineFunction &mf, LiveIntervals &lis, VirtRegAuxInfo(MachineFunction &mf, LiveIntervals &lis,
const MachineLoopInfo &loops) : const MachineLoopInfo &loops) :
mf_(mf), lis_(lis), loops_(loops) {} MF(mf), LIS(lis), Loops(loops) {}
/// CalculateRegClass - recompute the register class for reg from its uses. /// CalculateRegClass - recompute the register class for reg from its uses.
/// Since the register class can affect the allocation hint, this function /// Since the register class can affect the allocation hint, this function

81
lib/CodeGen/CalcSpillWeights.cpp
View File

@@ -87,8 +87,8 @@ static unsigned copyHint(const MachineInstr *mi, unsigned reg,
} }
void VirtRegAuxInfo::CalculateWeightAndHint(LiveInterval &li) { void VirtRegAuxInfo::CalculateWeightAndHint(LiveInterval &li) {
MachineRegisterInfo &mri = mf_.getRegInfo(); MachineRegisterInfo &mri = MF.getRegInfo();
const TargetRegisterInfo &tri = *mf_.getTarget().getRegisterInfo(); const TargetRegisterInfo &tri = *MF.getTarget().getRegisterInfo();
MachineBasicBlock *mbb = 0; MachineBasicBlock *mbb = 0;
MachineLoop *loop = 0; MachineLoop *loop = 0;
unsigned loopDepth = 0; unsigned loopDepth = 0;
@@ -118,7 +118,7 @@ void VirtRegAuxInfo::CalculateWeightAndHint(LiveInterval &li) {
// Get loop info for mi. // Get loop info for mi.
if (mi->getParent() != mbb) { if (mi->getParent() != mbb) {
mbb = mi->getParent(); mbb = mi->getParent();
loop = loops_.getLoopFor(mbb); loop = Loops.getLoopFor(mbb);
loopDepth = loop ? loop->getLoopDepth() : 0; loopDepth = loop ? loop->getLoopDepth() : 0;
isExiting = loop ? loop->isLoopExiting(mbb) : false; isExiting = loop ? loop->isLoopExiting(mbb) : false;
} }
@@ -129,7 +129,7 @@ void VirtRegAuxInfo::CalculateWeightAndHint(LiveInterval &li) {
weight = LiveIntervals::getSpillWeight(writes, reads, loopDepth); weight = LiveIntervals::getSpillWeight(writes, reads, loopDepth);
// Give extra weight to what looks like a loop induction variable update. // Give extra weight to what looks like a loop induction variable update.
if (writes && isExiting && lis_.isLiveOutOfMBB(li, mbb)) if (writes && isExiting && LIS.isLiveOutOfMBB(li, mbb))
weight *= 3; weight *= 3;
totalWeight += weight; totalWeight += weight;
@@ -141,9 +141,9 @@ void VirtRegAuxInfo::CalculateWeightAndHint(LiveInterval &li) {
unsigned hint = copyHint(mi, li.reg, tri, mri); unsigned hint = copyHint(mi, li.reg, tri, mri);
if (!hint) if (!hint)
continue; continue;
float hweight = hint_[hint] += weight; float hweight = Hint[hint] += weight;
if (TargetRegisterInfo::isPhysicalRegister(hint)) { if (TargetRegisterInfo::isPhysicalRegister(hint)) {
if (hweight > bestPhys && lis_.isAllocatable(hint)) if (hweight > bestPhys && LIS.isAllocatable(hint))
bestPhys = hweight, hintPhys = hint; bestPhys = hweight, hintPhys = hint;
} else { } else {
if (hweight > bestVirt) if (hweight > bestVirt)
@@ -151,7 +151,7 @@ void VirtRegAuxInfo::CalculateWeightAndHint(LiveInterval &li) {
} }
} }
hint_.clear(); Hint.clear();
// Always prefer the physreg hint. // Always prefer the physreg hint.
if (unsigned hint = hintPhys ? hintPhys : hintVirt) { if (unsigned hint = hintPhys ? hintPhys : hintVirt) {
@@ -176,7 +176,7 @@ void VirtRegAuxInfo::CalculateWeightAndHint(LiveInterval &li) {
// FIXME: this gets much more complicated once we support non-trivial // FIXME: this gets much more complicated once we support non-trivial
// re-materialization. // re-materialization.
bool isLoad = false; bool isLoad = false;
if (lis_.isReMaterializable(li, 0, isLoad)) { if (LIS.isReMaterializable(li, 0, isLoad)) {
if (isLoad) if (isLoad)
totalWeight *= 0.9F; totalWeight *= 0.9F;
else else
@@ -187,50 +187,29 @@ void VirtRegAuxInfo::CalculateWeightAndHint(LiveInterval &li) {
} }
void VirtRegAuxInfo::CalculateRegClass(unsigned reg) { void VirtRegAuxInfo::CalculateRegClass(unsigned reg) {
MachineRegisterInfo &mri = mf_.getRegInfo(); MachineRegisterInfo &MRI = MF.getRegInfo();
const TargetRegisterInfo *tri = mf_.getTarget().getRegisterInfo(); const TargetRegisterInfo *TRI = MF.getTarget().getRegisterInfo();
const TargetRegisterClass *orc = mri.getRegClass(reg); const TargetRegisterClass *OldRC = MRI.getRegClass(reg);
SmallPtrSet<const TargetRegisterClass*,8> rcs; const TargetRegisterClass *NewRC = TRI->getLargestLegalSuperClass(OldRC);
for (MachineRegisterInfo::reg_nodbg_iterator I = mri.reg_nodbg_begin(reg), // Stop early if there is no room to grow.
E = mri.reg_nodbg_end(); I != E; ++I) { if (NewRC == OldRC)
// The targets don't have accurate enough regclass descriptions that we can return;
// handle subregs. We need something similar to
// TRI::getMatchingSuperRegClass, but returning a super class instead of a // Accumulate constraints from all uses.
// sub class. for (MachineRegisterInfo::reg_nodbg_iterator I = MRI.reg_nodbg_begin(reg),
if (I.getOperand().getSubReg()) { E = MRI.reg_nodbg_end(); I != E; ++I) {
DEBUG(dbgs() << "Cannot handle subregs: " << I.getOperand() << '\n'); // TRI doesn't have accurate enough information to model this yet.
if (I.getOperand().getSubReg())
return;
const TargetRegisterClass *OpRC =
I->getDesc().getRegClass(I.getOperandNo(), TRI);
if (OpRC)
NewRC = getCommonSubClass(NewRC, OpRC);
if (!NewRC || NewRC == OldRC)
return; return;
}
if (const TargetRegisterClass *rc =
I->getDesc().getRegClass(I.getOperandNo(), tri))
rcs.insert(rc);
} }
DEBUG(dbgs() << "Inflating " << OldRC->getName() << ':' << PrintReg(reg)
// If we found no regclass constraints, just leave reg as is. << " to " << NewRC->getName() <<".\n");
// In theory, we could inflate to the largest superclass of reg's existing MRI.setRegClass(reg, NewRC);
// class, but that might not be legal for the current cpu setting.
// This could happen if reg is only used by COPY instructions, so we may need
// to improve on this.
if (rcs.empty()) {
return;
}
// Compute the intersection of all classes in rcs.
// This ought to be independent of iteration order, but if the target register
// classes don't form a proper algebra, it is possible to get different
// results. The solution is to make sure the intersection of any two register
// classes is also a register class or the null set.
const TargetRegisterClass *rc = 0;
for (SmallPtrSet<const TargetRegisterClass*,8>::iterator I = rcs.begin(),
E = rcs.end(); I != E; ++I) {
rc = rc ? getCommonSubClass(rc, *I) : *I;
assert(rc && "Incompatible regclass constraints found");
}
if (rc == orc)
return;
DEBUG(dbgs() << "Inflating " << orc->getName() << ':' << PrintReg(reg)
<< " to " << rc->getName() <<".\n");
mri.setRegClass(reg, rc);
} }