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Shift art to the right to keep GCC from complaining about multi-line comments.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84849 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Benjamin Kramer 2009-10-22 09:28:49 +00:00
parent 87689d3b70
commit 1395d1df09
1 changed files with 14 additions and 14 deletions
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28
lib/Target/MSP430/MSP430ISelDAGToDAG.cpp
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@ -165,10 +165,10 @@ bool MSP430DAGToDAGISel::IsLegalAndProfitableToFold(SDNode *N, SDNode *U,
if (OptLevel == CodeGenOpt::None) return false; if (OptLevel == CodeGenOpt::None) return false;
/// RMW preprocessing creates the following code: /// RMW preprocessing creates the following code:
/// [Load1] /// [Load1]
/// ^ ^ /// ^ ^
/// | \ /// / |
/// | \ /// / |
/// [Load2] | /// [Load2] |
/// ^ ^ | /// ^ ^ |
/// | | | /// | | |
@ -328,16 +328,16 @@ static bool isRMWLoad(SDValue N, SDValue Chain, SDValue Address,
/// We also recognize the case where second operand of Op is load as well and /// We also recognize the case where second operand of Op is load as well and
/// move it below token factor as well creating DAG as follows: /// move it below token factor as well creating DAG as follows:
/// ///
/// [Load chain] /// [Load chain]
/// ^ /// ^
/// | /// |
/// [TokenFactor] /// [TokenFactor]
/// ^ /// ^
/// | /// |
/// [Load1] /// [Load1]
/// ^ ^ /// ^ ^
/// | \ /// / |
/// | \ /// / |
/// [Load2] | /// [Load2] |
/// ^ ^ | /// ^ ^ |
/// | | | /// | | |