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Introducing plugable register allocators and instruction schedulers.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29434 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jim Laskey
2006-08-01 14:21:23 +00:00
parent 06c1e7eacb
commit 13ec702c43
14 changed files with 138 additions and 224 deletions
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5
lib/CodeGen/RegAllocSimple.cpp
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@@ -20,6 +20,7 @@
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/SSARegMap.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachinePassRegistry.h"
#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Support/Debug.h"
@@ -33,6 +34,10 @@ namespace {
static Statistic<> NumStores("ra-simple", "Number of stores added");
static Statistic<> NumLoads ("ra-simple", "Number of loads added");
static RegisterRegAlloc
simpleRegAlloc("simple", " simple register allocator",
createSimpleRegisterAllocator);
class VISIBILITY_HIDDEN RegAllocSimple : public MachineFunctionPass {
MachineFunction *MF;
const TargetMachine *TM;