6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-12-28 19:31:58 +00:00
Code Issues Projects Releases Wiki Activity

R600: Improve custom lowering of select_cc

Browse Source 
Two changes:
1. Prefer SET* instructions when possible
2. Handle the CND*_INT case with floating-point args

Reviewed-by: Christian König <christian.koenig@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176699 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Tom Stellard 2013-03-08 15:37:09 +00:00
parent d416505906
commit 1454cb86be
4 changed files with 82 additions and 40 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

67
lib/Target/R600/R600ISelLowering.cpp
View File

@ -542,12 +542,37 @@ SDValue R600TargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const
// Check if we can lower this to a native operation.
// Try to lower to a SET* instruction:
//
// SET* can match the following patterns:
//
// select_cc f32, f32, -1, 0, cc_any
// select_cc f32, f32, 1.0f, 0.0f, cc_any
// select_cc i32, i32, -1, 0, cc_any
//
// Move hardware True/False values to the correct operand.
if (isHWTrueValue(False) && isHWFalseValue(True)) {
ISD::CondCode CCOpcode = cast<CondCodeSDNode>(CC)->get();
std::swap(False, True);
CC = DAG.getCondCode(ISD::getSetCCInverse(CCOpcode, CompareVT == MVT::i32));
}
if (isHWTrueValue(True) && isHWFalseValue(False) &&
(CompareVT == VT || VT == MVT::i32)) {
// This can be matched by a SET* instruction.
return DAG.getNode(ISD::SELECT_CC, DL, VT, LHS, RHS, True, False, CC);
}
// Try to lower to a CND* instruction:
// CND* instructions requires RHS to be zero. Some SELECT_CC nodes that
// can be lowered to CND* instructions can also be lowered to SET*
// instructions. CND* instructions are cheaper, because they dont't
// require additional instructions to convert their result to the correct
// value type, so this check should be first.
//
// CND* can match the following patterns:
//
// select_cc f32, 0.0, f32, f32, cc_any
// select_cc f32, 0.0, i32, i32, cc_any
// select_cc i32, 0, f32, f32, cc_any
// select_cc i32, 0, i32, i32, cc_any
//
if (isZero(LHS) || isZero(RHS)) {
SDValue Cond = (isZero(LHS) ? RHS : LHS);
SDValue Zero = (isZero(LHS) ? LHS : RHS);
@ -589,38 +614,6 @@ SDValue R600TargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const
return DAG.getNode(ISD::BITCAST, DL, VT, SelectNode);
}
// Try to lower to a SET* instruction:
//
// CompareVT == MVT::f32 and VT == MVT::i32 is supported by the hardware,
// but for the other case where CompareVT != VT, all operands of
// SELECT_CC need to have the same value type, so we need to change True and
// False to be the same type as LHS and RHS, and then convert the result of
// the select_cc back to the correct type.
// Move hardware True/False values to the correct operand.
if (isHWTrueValue(False) && isHWFalseValue(True)) {
ISD::CondCode CCOpcode = cast<CondCodeSDNode>(CC)->get();
std::swap(False, True);
CC = DAG.getCondCode(ISD::getSetCCInverse(CCOpcode, CompareVT == MVT::i32));
}
if (isHWTrueValue(True) && isHWFalseValue(False)) {
if (CompareVT != VT && VT == MVT::f32 && CompareVT == MVT::i32) {
SDValue Boolean = DAG.getNode(ISD::SELECT_CC, DL, CompareVT,
LHS, RHS,
DAG.getConstant(-1, MVT::i32),
DAG.getConstant(0, MVT::i32),
CC);
// Convert integer values of true (-1) and false (0) to fp values of
// true (1.0f) and false (0.0f).
SDValue LSB = DAG.getNode(ISD::AND, DL, MVT::i32, Boolean,
DAG.getConstant(1, MVT::i32));
return DAG.getNode(ISD::UINT_TO_FP, DL, VT, LSB);
} else {
// This SELECT_CC is already legal.
return DAG.getNode(ISD::SELECT_CC, DL, VT, LHS, RHS, True, False, CC);
}
}
// Possible Min/Max pattern
SDValue MinMax = LowerMinMax(Op, DAG);

12
lib/Target/R600/R600Instructions.td
View File

@ -1840,6 +1840,18 @@ let isTerminator=1 in {
// ISel Patterns
//===----------------------------------------------------------------------===//
// CND*_INT Pattterns for f32 True / False values
class CND_INT_f32 <InstR600 cnd, CondCode cc> : Pat <
(selectcc (i32 R600_Reg32:$src0), 0, (f32 R600_Reg32:$src1),
R600_Reg32:$src2, cc),
(cnd R600_Reg32:$src0, R600_Reg32:$src1, R600_Reg32:$src2)
>;
def : CND_INT_f32 <CNDE_INT, SETEQ>;
def : CND_INT_f32 <CNDGT_INT, SETGT>;
def : CND_INT_f32 <CNDGE_INT, SETGE>;
//CNDGE_INT extra pattern
def : Pat <
(selectcc (i32 R600_Reg32:$src0), -1, (i32 R600_Reg32:$src1),

6
test/CodeGen/R600/fcmp-cnde-int-args.ll
View File

@ -1,10 +1,10 @@
;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
; This test checks a bug in R600TargetLowering::LowerSELECT_CC where the
; chance to optimize the fcmp + select instructions to CNDE was missed
; chance to optimize the fcmp + select instructions to SET* was missed
; due to the fact that the operands to fcmp and select had different types
;CHECK: CNDE T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], literal.x, 0.0, -1}}
; CHECK: SET{{[A-Z]+}}_DX10
define void @test(i32 addrspace(1)* %out, float addrspace(1)* %in) {
entry:

37
test/CodeGen/R600/selectcc-opt.ll Normal file
View File

@ -0,0 +1,37 @@
; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
; CHECK: @test_a
; CHECK-NOT: CND
; CHECK: SET{{[NEQGTL]+}}_DX10
define void @test_a(i32 addrspace(1)* %out, float %in) {
entry:
%0 = fcmp ult float %in, 0.000000e+00
%1 = select i1 %0, float 1.000000e+00, float 0.000000e+00
%2 = fsub float -0.000000e+00, %1
%3 = fptosi float %2 to i32
%4 = bitcast i32 %3 to float
%5 = bitcast float %4 to i32
%6 = icmp ne i32 %5, 0
br i1 %6, label %IF, label %ENDIF
IF:
%7 = getelementptr i32 addrspace(1)* %out, i32 1
store i32 0, i32 addrspace(1)* %7
br label %ENDIF
ENDIF:
store i32 0, i32 addrspace(1)* %out
ret void
}
; Test a CND*_INT instruction with float true/false values
; CHECK: @test_b
; CHECK: CND{{[GTE]+}}_INT
define void @test_b(float addrspace(1)* %out, i32 %in) {
entry:
%0 = icmp sgt i32 %in, 0
%1 = select i1 %0, float 2.0, float 3.0
store float %1, float addrspace(1)* %out
ret void
}