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[X86] Special-case 2x CMOV when custom-inserting.
This lets us avoid a few copies that are otherwise hard to get rid of. The way this is done is, the custom-inserter looks at the following instruction for another CMOV, and replaces both at the same time. A previous version used a new CMOV2 opcode, but the custom inserter is expected to be able to return a different basic block anyway, which means it's OK - though far from ideal - to alter that block's contents. Explicitly document that, in case it ever makes a difference. Alternatives welcome! Follow-up to r231045. rdar://19767934 Closes http://reviews.llvm.org/D8019 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@231046 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Ahmed Bougacha
parent
8b5527deef
commit
14593eb417
@ -2664,6 +2664,8 @@ public:
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/// is created but not inserted into any basic blocks, and this method is
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/// called to expand it into a sequence of instructions, potentially also
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/// creating new basic blocks and control flow.
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/// As long as the returned basic block is different (i.e., we created a new
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/// one), the custom inserter is free to modify the rest of \p MBB.
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virtual MachineBasicBlock *
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EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *MBB) const;
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@ -18108,6 +18108,92 @@ X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
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// fallthrough --> copy0MBB
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MachineBasicBlock *thisMBB = BB;
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MachineFunction *F = BB->getParent();
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// We also lower double CMOVs:
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// (CMOV (CMOV F, T, cc1), T, cc2)
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// to two successives branches. For that, we look for another CMOV as the
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// following instruction.
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//
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// Without this, we would add a PHI between the two jumps, which ends up
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// creating a few copies all around. For instance, for
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//
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// (sitofp (zext (fcmp une)))
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//
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// we would generate:
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//
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// ucomiss %xmm1, %xmm0
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// movss <1.0f>, %xmm0
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// movaps %xmm0, %xmm1
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// jne .LBB5_2
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// xorps %xmm1, %xmm1
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// .LBB5_2:
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// jp .LBB5_4
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// movaps %xmm1, %xmm0
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// .LBB5_4:
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// retq
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//
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// because this custom-inserter would have generated:
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//
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// A
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// | \
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// | B
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// | /
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// C
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// | \
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// | D
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// | /
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// E
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//
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// A: X = ...; Y = ...
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// B: empty
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// C: Z = PHI [X, A], [Y, B]
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// D: empty
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// E: PHI [X, C], [Z, D]
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//
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// If we lower both CMOVs in a single step, we can instead generate:
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//
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// A
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// | \
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// | C
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// | /|
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// |/ |
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// | |
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// | D
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// | /
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// E
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//
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// A: X = ...; Y = ...
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// D: empty
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// E: PHI [X, A], [X, C], [Y, D]
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//
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// Which, in our sitofp/fcmp example, gives us something like:
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//
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// ucomiss %xmm1, %xmm0
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// movss <1.0f>, %xmm0
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// jne .LBB5_4
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// jp .LBB5_4
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// xorps %xmm0, %xmm0
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// .LBB5_4:
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// retq
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//
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MachineInstr *NextCMOV = nullptr;
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MachineBasicBlock::iterator NextMIIt =
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std::next(MachineBasicBlock::iterator(MI));
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if (NextMIIt != BB->end() && NextMIIt->getOpcode() == MI->getOpcode() &&
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NextMIIt->getOperand(2).getReg() == MI->getOperand(2).getReg() &&
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NextMIIt->getOperand(1).getReg() == MI->getOperand(0).getReg())
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NextCMOV = &*NextMIIt;
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MachineBasicBlock *jcc1MBB = nullptr;
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// If we have a double CMOV, we lower it to two successive branches to
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// the same block. EFLAGS is used by both, so mark it as live in the second.
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if (NextCMOV) {
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jcc1MBB = F->CreateMachineBasicBlock(LLVM_BB);
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F->insert(It, jcc1MBB);
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jcc1MBB->addLiveIn(X86::EFLAGS);
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}
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MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
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MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
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F->insert(It, copy0MBB);
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@ -18116,8 +18202,10 @@ X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
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// If the EFLAGS register isn't dead in the terminator, then claim that it's
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// live into the sink and copy blocks.
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const TargetRegisterInfo *TRI = Subtarget->getRegisterInfo();
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if (!MI->killsRegister(X86::EFLAGS) &&
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!checkAndUpdateEFLAGSKill(MI, BB, TRI)) {
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MachineInstr *LastEFLAGSUser = NextCMOV ? NextCMOV : MI;
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if (!LastEFLAGSUser->killsRegister(X86::EFLAGS) &&
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!checkAndUpdateEFLAGSKill(LastEFLAGSUser, BB, TRI)) {
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copy0MBB->addLiveIn(X86::EFLAGS);
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sinkMBB->addLiveIn(X86::EFLAGS);
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}
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@ -18128,7 +18216,19 @@ X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
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sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
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// Add the true and fallthrough blocks as its successors.
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BB->addSuccessor(copy0MBB);
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if (NextCMOV) {
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// The fallthrough block may be jcc1MBB, if we have a double CMOV.
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BB->addSuccessor(jcc1MBB);
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// In that case, jcc1MBB will itself fallthrough the copy0MBB, and
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// jump to the sinkMBB.
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jcc1MBB->addSuccessor(copy0MBB);
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jcc1MBB->addSuccessor(sinkMBB);
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} else {
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BB->addSuccessor(copy0MBB);
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}
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// The true block target of the first (or only) branch is always sinkMBB.
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BB->addSuccessor(sinkMBB);
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// Create the conditional branch instruction.
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@ -18136,6 +18236,12 @@ X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
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X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
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BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
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if (NextCMOV) {
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unsigned Opc2 = X86::GetCondBranchFromCond(
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(X86::CondCode)NextCMOV->getOperand(3).getImm());
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BuildMI(jcc1MBB, DL, TII->get(Opc2)).addMBB(sinkMBB);
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}
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// copy0MBB:
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// %FalseValue = ...
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// # fallthrough to sinkMBB
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@ -18144,10 +18250,22 @@ X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
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// sinkMBB:
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// %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
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// ...
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BuildMI(*sinkMBB, sinkMBB->begin(), DL,
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TII->get(X86::PHI), MI->getOperand(0).getReg())
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.addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
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.addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
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MachineInstrBuilder MIB =
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BuildMI(*sinkMBB, sinkMBB->begin(), DL, TII->get(X86::PHI),
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MI->getOperand(0).getReg())
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.addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
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.addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
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// If we have a double CMOV, the second Jcc provides the same incoming
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// value as the first Jcc (the True operand of the SELECT_CC/CMOV nodes).
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if (NextCMOV) {
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MIB.addReg(MI->getOperand(2).getReg()).addMBB(jcc1MBB);
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// Copy the PHI result to the register defined by the second CMOV.
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BuildMI(*sinkMBB, std::next(MachineBasicBlock::iterator(MIB.getInstr())),
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DL, TII->get(TargetOpcode::COPY), NextCMOV->getOperand(0).getReg())
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.addReg(MI->getOperand(0).getReg());
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NextCMOV->eraseFromParent();
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}
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MI->eraseFromParent(); // The pseudo instruction is gone now.
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return sinkMBB;
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@ -15,21 +15,18 @@ target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"
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; CMOV-NEXT: movl %edi, %eax
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; CMOV-NEXT: retq
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; NOCMOV-NEXT: flds 8(%esp)
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; NOCMOV-NEXT: flds 4(%esp)
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; NOCMOV-NEXT: fucompp
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; NOCMOV-NEXT: fnstsw %ax
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; NOCMOV-NEXT: sahf
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; NOCMOV-NEXT: leal 16(%esp), %eax
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; NOCMOV-NEXT: movl %eax, %ecx
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; NOCMOV-NEXT: jne [[TBB1:.LBB[0-9_]+]]
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; NOCMOV-NEXT: leal 12(%esp), %ecx
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; NOCMOV-NEXT: [[TBB1]]:
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; NOCMOV-NEXT: jp [[TBB2:.LBB[0-9_]+]]
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; NOCMOV-NEXT: movl %ecx, %eax
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; NOCMOV-NEXT: [[TBB2]]:
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; NOCMOV-NEXT: movl (%eax), %eax
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; NOCMOV-NEXT: retl
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; NOCMOV-NEXT: flds 8(%esp)
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; NOCMOV-NEXT: flds 4(%esp)
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; NOCMOV-NEXT: fucompp
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; NOCMOV-NEXT: fnstsw %ax
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; NOCMOV-NEXT: sahf
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; NOCMOV-NEXT: leal 16(%esp), %eax
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; NOCMOV-NEXT: jne [[TBB:.LBB[0-9_]+]]
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; NOCMOV-NEXT: jp [[TBB]]
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; NOCMOV-NEXT: leal 12(%esp), %eax
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; NOCMOV-NEXT:[[TBB]]:
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; NOCMOV-NEXT: movl (%eax), %eax
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; NOCMOV-NEXT: retl
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define i32 @test_select_fcmp_oeq_i32(float %a, float %b, i32 %c, i32 %d) #0 {
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entry:
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%cmp = fcmp oeq float %a, %b
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@ -51,13 +48,10 @@ entry:
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; NOCMOV-NEXT: fnstsw %ax
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; NOCMOV-NEXT: sahf
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; NOCMOV-NEXT: leal 20(%esp), %ecx
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; NOCMOV-NEXT: movl %ecx, %eax
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; NOCMOV-NEXT: jne [[TBB1:.LBB[0-9_]+]]
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; NOCMOV-NEXT: leal 12(%esp), %eax
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; NOCMOV-NEXT: [[TBB1]]:
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; NOCMOV-NEXT: jp [[TBB2:.LBB[0-9_]+]]
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; NOCMOV-NEXT: movl %eax, %ecx
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; NOCMOV-NEXT: [[TBB2]]:
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; NOCMOV-NEXT: jne [[TBB:.LBB[0-9_]+]]
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; NOCMOV-NEXT: jp [[TBB]]
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; NOCMOV-NEXT: leal 12(%esp), %ecx
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; NOCMOV-NEXT: [[TBB]]:
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; NOCMOV-NEXT: movl (%ecx), %eax
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; NOCMOV-NEXT: orl $4, %ecx
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; NOCMOV-NEXT: movl (%ecx), %edx
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@ -83,13 +77,10 @@ entry:
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; NOCMOV-NEXT: fnstsw %ax
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; NOCMOV-NEXT: sahf
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; NOCMOV-NEXT: leal 12(%esp), %ecx
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; NOCMOV-NEXT: movl %ecx, %eax
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; NOCMOV-NEXT: jne [[TBB1:.LBB[0-9_]+]]
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; NOCMOV-NEXT: leal 20(%esp), %eax
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; NOCMOV-NEXT: [[TBB1]]:
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; NOCMOV-NEXT: jp [[TBB2:.LBB[0-9_]+]]
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; NOCMOV-NEXT: movl %eax, %ecx
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; NOCMOV-NEXT: [[TBB2]]:
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; NOCMOV-NEXT: jne [[TBB:.LBB[0-9_]+]]
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; NOCMOV-NEXT: jp [[TBB]]
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; NOCMOV-NEXT: leal 20(%esp), %ecx
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; NOCMOV-NEXT: [[TBB]]:
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; NOCMOV-NEXT: movl (%ecx), %eax
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; NOCMOV-NEXT: orl $4, %ecx
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; NOCMOV-NEXT: movl (%ecx), %edx
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@ -104,13 +95,10 @@ entry:
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; CHECK-LABEL: test_select_fcmp_oeq_f64:
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; CMOV-NEXT: ucomiss %xmm1, %xmm0
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; CMOV-NEXT: movaps %xmm3, %xmm0
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; CMOV-NEXT: jne [[TBB1:.LBB[0-9_]+]]
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; CMOV-NEXT: movaps %xmm2, %xmm0
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; CMOV-NEXT: [[TBB1]]:
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; CMOV-NEXT: jp [[TBB2:.LBB[0-9_]+]]
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; CMOV-NEXT: movaps %xmm0, %xmm3
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; CMOV-NEXT: [[TBB2]]:
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; CMOV-NEXT: jne [[TBB:.LBB[0-9_]+]]
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; CMOV-NEXT: jp [[TBB]]
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; CMOV-NEXT: movaps %xmm2, %xmm3
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; CMOV-NEXT: [[TBB]]:
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; CMOV-NEXT: movaps %xmm3, %xmm0
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; CMOV-NEXT: retq
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@ -120,13 +108,10 @@ entry:
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; NOCMOV-NEXT: fnstsw %ax
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; NOCMOV-NEXT: sahf
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; NOCMOV-NEXT: leal 20(%esp), %eax
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; NOCMOV-NEXT: movl %eax, %ecx
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; NOCMOV-NEXT: jne [[TBB1:.LBB[0-9_]+]]
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; NOCMOV-NEXT: leal 12(%esp), %ecx
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; NOCMOV-NEXT: [[TBB1]]:
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; NOCMOV-NEXT: jp [[TBB2:.LBB[0-9_]+]]
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; NOCMOV-NEXT: movl %ecx, %eax
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; NOCMOV-NEXT: [[TBB2]]:
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; NOCMOV-NEXT: jne [[TBB:.LBB[0-9_]+]]
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; NOCMOV-NEXT: jp [[TBB]]
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; NOCMOV-NEXT: leal 12(%esp), %eax
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; NOCMOV-NEXT: [[TBB]]:
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; NOCMOV-NEXT: fldl (%eax)
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; NOCMOV-NEXT: retl
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define double @test_select_fcmp_oeq_f64(float %a, float %b, double %c, double %d) #0 {
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@ -139,68 +124,51 @@ entry:
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; CHECK-LABEL: test_select_fcmp_oeq_v4i32:
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; CMOV-NEXT: ucomiss %xmm1, %xmm0
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; CMOV-NEXT: movaps %xmm3, %xmm0
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; CMOV-NEXT: jne [[TBB1:.LBB[0-9_]+]]
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; CMOV-NEXT: movaps %xmm2, %xmm0
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; CMOV-NEXT: [[TBB1]]:
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; CMOV-NEXT: jp [[TBB2:.LBB[0-9_]+]]
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; CMOV-NEXT: movaps %xmm0, %xmm3
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; CMOV-NEXT: [[TBB2]]:
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; CMOV-NEXT: jne [[TBB:.LBB[0-9_]+]]
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; CMOV-NEXT: jp [[TBB]]
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; CMOV-NEXT: movaps %xmm2, %xmm3
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; CMOV-NEXT: [[TBB]]:
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; CMOV-NEXT: movaps %xmm3, %xmm0
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; CMOV-NEXT: retq
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; NOCMOV-NEXT: pushl %ebx
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; NOCMOV-NEXT: pushl %edi
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; NOCMOV-NEXT: pushl %esi
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; NOCMOV-NEXT: flds 24(%esp)
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; NOCMOV-NEXT: flds 20(%esp)
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; NOCMOV-NEXT: flds 16(%esp)
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; NOCMOV-NEXT: fucompp
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; NOCMOV-NEXT: fnstsw %ax
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; NOCMOV-NEXT: sahf
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; NOCMOV-NEXT: leal 44(%esp), %eax
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; NOCMOV-NEXT: movl %eax, %ecx
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; NOCMOV-NEXT: jne [[TBB1:.LBB[0-9_]+]]
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; NOCMOV-NEXT: leal 28(%esp), %ecx
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; NOCMOV-NEXT: [[TBB1]]:
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; NOCMOV-NEXT: jp [[TBB2:.LBB[0-9_]+]]
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; NOCMOV-NEXT: movl %ecx, %eax
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; NOCMOV-NEXT: [[TBB2]]:
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; NOCMOV-NEXT: leal 40(%esp), %eax
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; NOCMOV-NEXT: jne [[TBB:.LBB[0-9_]+]]
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; NOCMOV-NEXT: jp [[TBB]]
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; NOCMOV-NEXT: leal 24(%esp), %eax
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; NOCMOV-NEXT: [[TBB]]:
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; NOCMOV-NEXT: movl (%eax), %eax
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; NOCMOV-NEXT: leal 48(%esp), %ecx
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; NOCMOV-NEXT: movl %ecx, %edx
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; NOCMOV-NEXT: jne [[TBB1:.LBB[0-9_]+]]
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; NOCMOV-NEXT: leal 32(%esp), %edx
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; NOCMOV-NEXT: [[TBB1]]:
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; NOCMOV-NEXT: jp [[TBB2:.LBB[0-9_]+]]
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; NOCMOV-NEXT: movl %edx, %ecx
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; NOCMOV-NEXT: [[TBB2]]:
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; NOCMOV-NEXT: leal 44(%esp), %ecx
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; NOCMOV-NEXT: jne [[TBB:.LBB[0-9_]+]]
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; NOCMOV-NEXT: jp [[TBB]]
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; NOCMOV-NEXT: leal 28(%esp), %ecx
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; NOCMOV-NEXT: [[TBB]]:
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; NOCMOV-NEXT: movl (%ecx), %ecx
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; NOCMOV-NEXT: leal 52(%esp), %edx
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; NOCMOV-NEXT: movl %edx, %esi
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; NOCMOV-NEXT: jne [[TBB1:.LBB[0-9_]+]]
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; NOCMOV-NEXT: leal 36(%esp), %esi
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; NOCMOV-NEXT: [[TBB1]]:
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; NOCMOV-NEXT: jp [[TBB2:.LBB[0-9_]+]]
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; NOCMOV-NEXT: movl %esi, %edx
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; NOCMOV-NEXT: [[TBB2]]:
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; NOCMOV-NEXT: movl (%edx), %edx
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; NOCMOV-NEXT: leal 56(%esp), %esi
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; NOCMOV-NEXT: movl %esi, %ebx
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; NOCMOV-NEXT: jne [[TBB1:.LBB[0-9_]+]]
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; NOCMOV-NEXT: leal 40(%esp), %ebx
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; NOCMOV-NEXT: [[TBB1]]:
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; NOCMOV-NEXT: movl 16(%esp), %edi
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; NOCMOV-NEXT: jp [[TBB2:.LBB[0-9_]+]]
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; NOCMOV-NEXT: movl %ebx, %esi
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; NOCMOV-NEXT: [[TBB2]]:
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; NOCMOV-NEXT: leal 48(%esp), %esi
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; NOCMOV-NEXT: jne [[TBB:.LBB[0-9_]+]]
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; NOCMOV-NEXT: jp [[TBB]]
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; NOCMOV-NEXT: leal 32(%esp), %esi
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; NOCMOV-NEXT: [[TBB]]:
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; NOCMOV-NEXT: movl 12(%esp), %edx
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; NOCMOV-NEXT: movl (%esi), %esi
|
||||
; NOCMOV-NEXT: movl %esi, 12(%edi)
|
||||
; NOCMOV-NEXT: movl %edx, 8(%edi)
|
||||
; NOCMOV-NEXT: movl %ecx, 4(%edi)
|
||||
; NOCMOV-NEXT: movl %eax, (%edi)
|
||||
; NOCMOV-NEXT: leal 52(%esp), %edi
|
||||
; NOCMOV-NEXT: jne [[TBB:.LBB[0-9_]+]]
|
||||
; NOCMOV-NEXT: jp [[TBB]]
|
||||
; NOCMOV-NEXT: leal 36(%esp), %edi
|
||||
; NOCMOV-NEXT: [[TBB]]:
|
||||
; NOCMOV-NEXT: movl (%edi), %edi
|
||||
; NOCMOV-NEXT: movl %edi, 12(%edx)
|
||||
; NOCMOV-NEXT: movl %esi, 8(%edx)
|
||||
; NOCMOV-NEXT: movl %ecx, 4(%edx)
|
||||
; NOCMOV-NEXT: movl %eax, (%edx)
|
||||
; NOCMOV-NEXT: popl %esi
|
||||
; NOCMOV-NEXT: popl %edi
|
||||
; NOCMOV-NEXT: popl %ebx
|
||||
; NOCMOV-NEXT: retl $4
|
||||
define <4 x i32> @test_select_fcmp_oeq_v4i32(float %a, float %b, <4 x i32> %c, <4 x i32> %d) #0 {
|
||||
entry:
|
||||
@ -217,17 +185,14 @@ entry:
|
||||
; CHECK-LABEL: test_zext_fcmp_une:
|
||||
; CMOV-NEXT: ucomiss %xmm1, %xmm0
|
||||
; CMOV-NEXT: movss [[ONE_F32_LCPI]](%rip), %xmm0
|
||||
; CMOV-NEXT: movaps %xmm0, %xmm1
|
||||
; CMOV-NEXT: jne [[TBB1:.LBB[0-9_]+]]
|
||||
; CMOV-NEXT: xorps %xmm1, %xmm1
|
||||
; CMOV-NEXT: [[TBB1]]:
|
||||
; CMOV-NEXT: jp [[TBB2:.LBB[0-9_]+]]
|
||||
; CMOV-NEXT: movaps %xmm1, %xmm0
|
||||
; CMOV-NEXT: [[TBB2]]:
|
||||
; CMOV-NEXT: jne [[TBB:.LBB[0-9_]+]]
|
||||
; CMOV-NEXT: jp [[TBB]]
|
||||
; CMOV-NEXT: xorps %xmm0, %xmm0
|
||||
; CMOV-NEXT: [[TBB]]:
|
||||
; CMOV-NEXT: retq
|
||||
|
||||
; NOCMOV: jne
|
||||
; NOCMOV: jp
|
||||
; NOCMOV: jne
|
||||
; NOCMOV-NEXT: jp
|
||||
define float @test_zext_fcmp_une(float %a, float %b) #0 {
|
||||
entry:
|
||||
%cmp = fcmp une float %a, %b
|
||||
@ -242,17 +207,14 @@ entry:
|
||||
; CHECK-LABEL: test_zext_fcmp_oeq:
|
||||
; CMOV-NEXT: ucomiss %xmm1, %xmm0
|
||||
; CMOV-NEXT: xorps %xmm0, %xmm0
|
||||
; CMOV-NEXT: xorps %xmm1, %xmm1
|
||||
; CMOV-NEXT: jne [[TBB1:.LBB[0-9_]+]]
|
||||
; CMOV-NEXT: movss [[ONE_F32_LCPI]](%rip), %xmm1
|
||||
; CMOV-NEXT: [[TBB1]]:
|
||||
; CMOV-NEXT: jp [[TBB2:.LBB[0-9_]+]]
|
||||
; CMOV-NEXT: movaps %xmm1, %xmm0
|
||||
; CMOV-NEXT: [[TBB2]]:
|
||||
; CMOV-NEXT: jne [[TBB:.LBB[0-9_]+]]
|
||||
; CMOV-NEXT: jp [[TBB]]
|
||||
; CMOV-NEXT: movss [[ONE_F32_LCPI]](%rip), %xmm0
|
||||
; CMOV-NEXT: [[TBB]]:
|
||||
; CMOV-NEXT: retq
|
||||
|
||||
; NOCMOV: jne
|
||||
; NOCMOV: jp
|
||||
; NOCMOV: jne
|
||||
; NOCMOV-NEXT: jp
|
||||
define float @test_zext_fcmp_oeq(float %a, float %b) #0 {
|
||||
entry:
|
||||
%cmp = fcmp oeq float %a, %b
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user