6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-12-26 05:32:25 +00:00
Code Issues Projects Releases Wiki Activity

Fix for PR18921 (LDRD/STRD part)::

Browse Source 
Removed "GNU Assembler extension (compatibility)" definitions from ARMInstrInfo.td
Fixed ARMAsmParser::ParseInstruction GNU compatability branch, so it also works for thumb mode from now.
Added new tests.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205622 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Stepan Dyatkovskiy 2014-04-04 10:17:56 +00:00
parent 0670d7e47a
commit 148692bafe
6 changed files with 73 additions and 25 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

14
lib/Target/ARM/ARMInstrInfo.td
View File

@ -2282,12 +2282,6 @@ let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
def LDRD : AI3ld<0b1101, 0, (outs GPR:$Rt, GPR:$Rt2), (ins addrmode3:$addr),
LdMiscFrm, IIC_iLoad_d_r, "ldrd", "\t$Rt, $Rt2, $addr", []>,
Requires<[IsARM, HasV5TE]>;
// GNU Assembler extension (compatibility)
let isAsmParserOnly = 1 in
def LDRD_PAIR : AI3ld<0b1101, 0, (outs GPRPairOp:$Rt), (ins addrmode3:$addr),
LdMiscFrm, IIC_iLoad_d_r, "ldrd", "\t$Rt, $addr", []>,
Requires<[IsARM, HasV5TE]>;
}
def LDA : AIldracq<0b00, (outs GPR:$Rt), (ins addr_offset_none:$addr),
@ -2557,14 +2551,6 @@ let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in {
Requires<[IsARM, HasV5TE]> {
let Inst{21} = 0;
}
// GNU Assembler extension (compatibility)
let isAsmParserOnly = 1 in
def STRD_PAIR : AI3str<0b1111, (outs), (ins GPRPairOp:$Rt, addrmode3:$addr),
StMiscFrm, IIC_iStore_d_r, "strd", "\t$Rt, $addr", []>,
Requires<[IsARM, HasV5TE]> {
let Inst{21} = 0;
}
}
// Indexed stores

25
lib/Target/ARM/AsmParser/ARMAsmParser.cpp
View File

@ -5404,21 +5404,24 @@ bool ARMAsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
}
// GNU Assembler extension (compatibility)
if ((Mnemonic == "ldrd" || Mnemonic == "strd") && !isThumb() &&
Operands.size() == 4) {
ARMOperand *Op = static_cast<ARMOperand *>(Operands[2]);
assert(Op->isReg() && "expected register argument");
if ((Mnemonic == "ldrd" || Mnemonic == "strd")) {
ARMOperand *Op2 = static_cast<ARMOperand *>(Operands[2]);
ARMOperand *Op3 = static_cast<ARMOperand *>(Operands[3]);
if (Op3->isMem()) {
assert(Op2->isReg() && "expected register argument");
unsigned SuperReg = MRI->getMatchingSuperReg(
Op->getReg(), ARM::gsub_0, &MRI->getRegClass(ARM::GPRPairRegClassID));
unsigned SuperReg = MRI->getMatchingSuperReg(
Op2->getReg(), ARM::gsub_0, &MRI->getRegClass(ARM::GPRPairRegClassID));
assert(SuperReg && "expected register pair");
assert(SuperReg && "expected register pair");
unsigned PairedReg = MRI->getSubReg(SuperReg, ARM::gsub_1);
unsigned PairedReg = MRI->getSubReg(SuperReg, ARM::gsub_1);
Operands.insert(Operands.begin() + 3,
ARMOperand::CreateReg(PairedReg, Op->getStartLoc(),
Op->getEndLoc()));
Operands.insert(Operands.begin() + 3,
ARMOperand::CreateReg(PairedReg,
Op2->getStartLoc(),
Op2->getEndLoc()));
}
}
// FIXME: As said above, this is all a pretty gross hack. This instruction

9
test/MC/ARM/ldrd-strd-gnu-arm-bad-imm.s Normal file
View File

@ -0,0 +1,9 @@
@ RUN: not llvm-mc -triple=armv7-linux-gnueabi %s 2>&1 | FileCheck %s
.text
@ CHECK: error: instruction requires: thumb2
@ CHECK: ldrd r0, [r0, #512]
ldrd r0, [r0, #512]
@ CHECK: error: instruction requires: thumb2
@ CHECK: strd r0, [r0, #512]
strd r0, [r0, #512]

20
test/MC/ARM/ldrd-strd-gnu-arm.s Normal file
View File

@ -0,0 +1,20 @@
@ PR18921
@ RUN: llvm-mc -triple=armv7-linux-gnueabi -show-encoding < %s | FileCheck %s
.text
@ CHECK-NOT: .code 16
@ CHECK: ldrd r0, r1, [r10, #32]! @ encoding: [0xd0,0x02,0xea,0xe1]
@ CHECK: ldrd r0, r1, [r10], #32 @ encoding: [0xd0,0x02,0xca,0xe0]
@ CHECK: ldrd r0, r1, [r10, #32] @ encoding: [0xd0,0x02,0xca,0xe1]
ldrd r0, [r10, #32]!
ldrd r0, [r10], #32
ldrd r0, [r10, #32]
@ CHECK: strd r0, r1, [r10, #32]! @ encoding: [0xf0,0x02,0xea,0xe1]
@ CHECK: strd r0, r1, [r10], #32 @ encoding: [0xf0,0x02,0xca,0xe0]
@ CHECK: strd r0, r1, [r10, #32] @ encoding: [0xf0,0x02,0xca,0xe1]
strd r0, [r10, #32]!
strd r0, [r10], #32
strd r0, [r10, #32]

10
test/MC/ARM/ldrd-strd-gnu-thumb-bad-regs.s Normal file
View File

@ -0,0 +1,10 @@
@ RUN: not llvm-mc -triple=armv7-linux-gnueabi %s 2>&1 | FileCheck %s
.text
.thumb
@ CHECK: error: invalid operand for instruction
@ CHECK: ldrd r12, [r0, #512]
ldrd r12, [r0, #512]
@ CHECK: error: invalid operand for instruction
@ CHECK: strd r12, [r0, #512]
strd r12, [r0, #512]

20
test/MC/ARM/ldrd-strd-gnu-thumb.s Normal file
View File

@ -0,0 +1,20 @@
@ PR18921
@ RUN: llvm-mc -triple=armv7-linux-gnueabi -show-encoding < %s | FileCheck %s
.text
.thumb
@ CHECK: .code 16
@ CHECK: ldrd r0, r1, [r10, #512]! @ encoding: [0xfa,0xe9,0x80,0x01]
@ CHECK: ldrd r0, r1, [r10], #512 @ encoding: [0xfa,0xe8,0x80,0x01]
@ CHECK: ldrd r0, r1, [r10, #512] @ encoding: [0xda,0xe9,0x80,0x01]
ldrd r0, [r10, #512]!
ldrd r0, [r10], #512
ldrd r0, [r10, #512]
@ CHECK: strd r0, r1, [r10, #512]! @ encoding: [0xea,0xe9,0x80,0x01]
@ CHECK: strd r0, r1, [r10], #512 @ encoding: [0xea,0xe8,0x80,0x01]
@ CHECK: strd r0, r1, [r10, #512] @ encoding: [0xca,0xe9,0x80,0x01]
strd r0, [r10, #512]!
strd r0, [r10], #512
strd r0, [r10, #512]