mirror of
https://github.com/c64scene-ar/llvm-6502.git
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Use direct types in PowerPC Pat patterns.
This commit updates the PowerPC back-end (PPCInstrInfo.td and PPCInstr64Bit.td) to use types instead of register classes in Pat patterns, along the lines of Jakob Stoklund Olesen's changes in r177829 for Sparc. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177889 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Ulrich Weigand
parent
9b3939983f
commit
1492a4e518
@ -709,8 +709,8 @@ def LDgotTprelL: Pseudo<(outs G8RC:$rD), (ins symbolLo64:$disp, G8RC:$reg),
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[(set G8RC:$rD,
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(PPCldGotTprelL tglobaltlsaddr:$disp, G8RC:$reg))]>,
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isPPC64;
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def : Pat<(PPCaddTls G8RC:$in, tglobaltlsaddr:$g),
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(ADD8TLS G8RC:$in, tglobaltlsaddr:$g)>;
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def : Pat<(PPCaddTls i64:$in, tglobaltlsaddr:$g),
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(ADD8TLS $in, tglobaltlsaddr:$g)>;
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def ADDIStlsgdHA: Pseudo<(outs G8RC:$rD), (ins G8RC:$reg, symbolHi64:$disp),
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"#ADDIStlsgdHA",
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[(set G8RC:$rD,
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@ -831,23 +831,23 @@ def STDUX : XForm_8<31, 181, (outs ptr_rc_nor0:$ea_res), (ins G8RC:$rS, memrr:$d
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// Patterns to match the pre-inc stores. We can't put the patterns on
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// the instruction definitions directly as ISel wants the address base
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// and offset to be separate operands, not a single complex operand.
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def : Pat<(pre_truncsti8 G8RC:$rS, ptr_rc_nor0:$ptrreg, iaddroff:$ptroff),
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(STBU8 G8RC:$rS, iaddroff:$ptroff, ptr_rc_nor0:$ptrreg)>;
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def : Pat<(pre_truncsti16 G8RC:$rS, ptr_rc_nor0:$ptrreg, iaddroff:$ptroff),
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(STHU8 G8RC:$rS, iaddroff:$ptroff, ptr_rc_nor0:$ptrreg)>;
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def : Pat<(pre_truncsti32 G8RC:$rS, ptr_rc_nor0:$ptrreg, iaddroff:$ptroff),
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(STWU8 G8RC:$rS, iaddroff:$ptroff, ptr_rc_nor0:$ptrreg)>;
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def : Pat<(aligned4pre_store G8RC:$rS, ptr_rc_nor0:$ptrreg, iaddroff:$ptroff),
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(STDU G8RC:$rS, iaddroff:$ptroff, ptr_rc_nor0:$ptrreg)>;
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def : Pat<(pre_truncsti8 i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
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(STBU8 $rS, iaddroff:$ptroff, $ptrreg)>;
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def : Pat<(pre_truncsti16 i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
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(STHU8 $rS, iaddroff:$ptroff, $ptrreg)>;
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def : Pat<(pre_truncsti32 i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
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(STWU8 $rS, iaddroff:$ptroff, $ptrreg)>;
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def : Pat<(aligned4pre_store i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
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(STDU $rS, iaddroff:$ptroff, $ptrreg)>;
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def : Pat<(pre_truncsti8 G8RC:$rS, ptr_rc_nor0:$ptrreg, ptr_rc:$ptroff),
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(STBUX8 G8RC:$rS, ptr_rc_nor0:$ptrreg, ptr_rc:$ptroff)>;
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def : Pat<(pre_truncsti16 G8RC:$rS, ptr_rc_nor0:$ptrreg, ptr_rc:$ptroff),
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(STHUX8 G8RC:$rS, ptr_rc_nor0:$ptrreg, ptr_rc:$ptroff)>;
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def : Pat<(pre_truncsti32 G8RC:$rS, ptr_rc_nor0:$ptrreg, ptr_rc:$ptroff),
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(STWUX8 G8RC:$rS, ptr_rc_nor0:$ptrreg, ptr_rc:$ptroff)>;
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def : Pat<(pre_store G8RC:$rS, ptr_rc_nor0:$ptrreg, ptr_rc:$ptroff),
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(STDUX G8RC:$rS, ptr_rc_nor0:$ptrreg, ptr_rc:$ptroff)>;
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def : Pat<(pre_truncsti8 i64:$rS, iPTR:$ptrreg, iPTR:$ptroff),
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(STBUX8 $rS, $ptrreg, $ptroff)>;
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def : Pat<(pre_truncsti16 i64:$rS, iPTR:$ptrreg, iPTR:$ptroff),
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(STHUX8 $rS, $ptrreg, $ptroff)>;
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def : Pat<(pre_truncsti32 i64:$rS, iPTR:$ptrreg, iPTR:$ptroff),
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(STWUX8 $rS, $ptrreg, $ptroff)>;
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def : Pat<(pre_store i64:$rS, iPTR:$ptrreg, iPTR:$ptroff),
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(STDUX $rS, $ptrreg, $ptroff)>;
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//===----------------------------------------------------------------------===//
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@ -870,13 +870,13 @@ def FCTIDZ : XForm_26<63, 815, (outs F8RC:$frD), (ins F8RC:$frB),
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//
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// Extensions and truncates to/from 32-bit regs.
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def : Pat<(i64 (zext GPRC:$in)),
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(RLDICL (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPRC:$in, sub_32),
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def : Pat<(i64 (zext i32:$in)),
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(RLDICL (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $in, sub_32),
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0, 32)>;
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def : Pat<(i64 (anyext GPRC:$in)),
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(INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPRC:$in, sub_32)>;
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def : Pat<(i32 (trunc G8RC:$in)),
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(EXTRACT_SUBREG G8RC:$in, sub_32)>;
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def : Pat<(i64 (anyext i32:$in)),
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(INSERT_SUBREG (i64 (IMPLICIT_DEF)), $in, sub_32)>;
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def : Pat<(i32 (trunc i64:$in)),
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(EXTRACT_SUBREG $in, sub_32)>;
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// Extending loads with i64 targets.
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def : Pat<(zextloadi1 iaddr:$src),
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@ -903,24 +903,24 @@ def : Pat<(extloadi32 xaddr:$src),
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// Standard shifts. These are represented separately from the real shifts above
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// so that we can distinguish between shifts that allow 6-bit and 7-bit shift
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// amounts.
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def : Pat<(sra G8RC:$rS, GPRC:$rB),
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(SRAD G8RC:$rS, GPRC:$rB)>;
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def : Pat<(srl G8RC:$rS, GPRC:$rB),
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(SRD G8RC:$rS, GPRC:$rB)>;
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def : Pat<(shl G8RC:$rS, GPRC:$rB),
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(SLD G8RC:$rS, GPRC:$rB)>;
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def : Pat<(sra i64:$rS, i32:$rB),
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(SRAD $rS, $rB)>;
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def : Pat<(srl i64:$rS, i32:$rB),
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(SRD $rS, $rB)>;
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def : Pat<(shl i64:$rS, i32:$rB),
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(SLD $rS, $rB)>;
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// SHL/SRL
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def : Pat<(shl G8RC:$in, (i32 imm:$imm)),
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(RLDICR G8RC:$in, imm:$imm, (SHL64 imm:$imm))>;
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def : Pat<(srl G8RC:$in, (i32 imm:$imm)),
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(RLDICL G8RC:$in, (SRL64 imm:$imm), imm:$imm)>;
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def : Pat<(shl i64:$in, (i32 imm:$imm)),
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(RLDICR $in, imm:$imm, (SHL64 imm:$imm))>;
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def : Pat<(srl i64:$in, (i32 imm:$imm)),
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(RLDICL $in, (SRL64 imm:$imm), imm:$imm)>;
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// ROTL
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def : Pat<(rotl G8RC:$in, GPRC:$sh),
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(RLDCL G8RC:$in, GPRC:$sh, 0)>;
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def : Pat<(rotl G8RC:$in, (i32 imm:$imm)),
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(RLDICL G8RC:$in, imm:$imm, 0)>;
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def : Pat<(rotl i64:$in, i32:$sh),
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(RLDCL $in, $sh, 0)>;
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def : Pat<(rotl i64:$in, (i32 imm:$imm)),
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(RLDICL $in, imm:$imm, 0)>;
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// Hi and Lo for Darwin Global Addresses.
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def : Pat<(PPChi tglobaladdr:$in, 0), (LIS8 tglobaladdr:$in)>;
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@ -931,18 +931,18 @@ def : Pat<(PPChi tjumptable:$in , 0), (LIS8 tjumptable:$in)>;
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def : Pat<(PPClo tjumptable:$in , 0), (LI8 tjumptable:$in)>;
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def : Pat<(PPChi tblockaddress:$in, 0), (LIS8 tblockaddress:$in)>;
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def : Pat<(PPClo tblockaddress:$in, 0), (LI8 tblockaddress:$in)>;
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def : Pat<(PPChi tglobaltlsaddr:$g, G8RC:$in),
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(ADDIS8 G8RC:$in, tglobaltlsaddr:$g)>;
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def : Pat<(PPClo tglobaltlsaddr:$g, G8RC:$in),
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(ADDI8L G8RC:$in, tglobaltlsaddr:$g)>;
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def : Pat<(add G8RC:$in, (PPChi tglobaladdr:$g, 0)),
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(ADDIS8 G8RC:$in, tglobaladdr:$g)>;
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def : Pat<(add G8RC:$in, (PPChi tconstpool:$g, 0)),
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(ADDIS8 G8RC:$in, tconstpool:$g)>;
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def : Pat<(add G8RC:$in, (PPChi tjumptable:$g, 0)),
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(ADDIS8 G8RC:$in, tjumptable:$g)>;
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def : Pat<(add G8RC:$in, (PPChi tblockaddress:$g, 0)),
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(ADDIS8 G8RC:$in, tblockaddress:$g)>;
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def : Pat<(PPChi tglobaltlsaddr:$g, i64:$in),
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(ADDIS8 $in, tglobaltlsaddr:$g)>;
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def : Pat<(PPClo tglobaltlsaddr:$g, i64:$in),
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(ADDI8L $in, tglobaltlsaddr:$g)>;
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def : Pat<(add i64:$in, (PPChi tglobaladdr:$g, 0)),
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(ADDIS8 $in, tglobaladdr:$g)>;
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def : Pat<(add i64:$in, (PPChi tconstpool:$g, 0)),
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(ADDIS8 $in, tconstpool:$g)>;
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def : Pat<(add i64:$in, (PPChi tjumptable:$g, 0)),
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(ADDIS8 $in, tjumptable:$g)>;
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def : Pat<(add i64:$in, (PPChi tblockaddress:$g, 0)),
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(ADDIS8 $in, tblockaddress:$g)>;
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// Patterns to match r+r indexed loads and stores for
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// addresses without at least 4-byte alignment.
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@ -950,6 +950,6 @@ def : Pat<(i64 (unaligned4sextloadi32 xoaddr:$src)),
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(LWAX xoaddr:$src)>;
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def : Pat<(i64 (unaligned4load xoaddr:$src)),
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(LDX xoaddr:$src)>;
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def : Pat<(unaligned4store G8RC:$rS, xoaddr:$dst),
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(STDX G8RC:$rS, xoaddr:$dst)>;
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def : Pat<(unaligned4store i64:$rS, xoaddr:$dst),
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(STDX $rS, xoaddr:$dst)>;
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@ -896,16 +896,16 @@ def STFDU : DForm_1<37, (outs ptr_rc_nor0:$ea_res), (ins F8RC:$rS, memri:$dst),
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// Patterns to match the pre-inc stores. We can't put the patterns on
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// the instruction definitions directly as ISel wants the address base
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// and offset to be separate operands, not a single complex operand.
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def : Pat<(pre_truncsti8 GPRC:$rS, ptr_rc_nor0:$ptrreg, iaddroff:$ptroff),
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(STBU GPRC:$rS, iaddroff:$ptroff, ptr_rc_nor0:$ptrreg)>;
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def : Pat<(pre_truncsti16 GPRC:$rS, ptr_rc_nor0:$ptrreg, iaddroff:$ptroff),
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(STHU GPRC:$rS, iaddroff:$ptroff, ptr_rc_nor0:$ptrreg)>;
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def : Pat<(pre_store GPRC:$rS, ptr_rc_nor0:$ptrreg, iaddroff:$ptroff),
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(STWU GPRC:$rS, iaddroff:$ptroff, ptr_rc_nor0:$ptrreg)>;
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def : Pat<(pre_store F4RC:$rS, ptr_rc_nor0:$ptrreg, iaddroff:$ptroff),
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(STFSU F4RC:$rS, iaddroff:$ptroff, ptr_rc_nor0:$ptrreg)>;
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def : Pat<(pre_store F8RC:$rS, ptr_rc_nor0:$ptrreg, iaddroff:$ptroff),
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(STFDU F8RC:$rS, iaddroff:$ptroff, ptr_rc_nor0:$ptrreg)>;
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def : Pat<(pre_truncsti8 i32:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
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(STBU $rS, iaddroff:$ptroff, $ptrreg)>;
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def : Pat<(pre_truncsti16 i32:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
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(STHU $rS, iaddroff:$ptroff, $ptrreg)>;
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def : Pat<(pre_store i32:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
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(STWU $rS, iaddroff:$ptroff, $ptrreg)>;
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def : Pat<(pre_store f32:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
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(STFSU $rS, iaddroff:$ptroff, $ptrreg)>;
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def : Pat<(pre_store f64:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
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(STFDU $rS, iaddroff:$ptroff, $ptrreg)>;
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// Indexed (r+r) Stores.
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let PPC970_Unit = 2 in {
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@ -970,16 +970,16 @@ def STFDUX: XForm_8<31, 759, (outs ptr_rc_nor0:$ea_res), (ins F8RC:$rS, memrr:$d
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// Patterns to match the pre-inc stores. We can't put the patterns on
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// the instruction definitions directly as ISel wants the address base
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// and offset to be separate operands, not a single complex operand.
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def : Pat<(pre_truncsti8 GPRC:$rS, ptr_rc_nor0:$ptrreg, ptr_rc:$ptroff),
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(STBUX GPRC:$rS, ptr_rc_nor0:$ptrreg, ptr_rc:$ptroff)>;
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def : Pat<(pre_truncsti16 GPRC:$rS, ptr_rc_nor0:$ptrreg, ptr_rc:$ptroff),
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(STHUX GPRC:$rS, ptr_rc_nor0:$ptrreg, ptr_rc:$ptroff)>;
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def : Pat<(pre_store GPRC:$rS, ptr_rc_nor0:$ptrreg, ptr_rc:$ptroff),
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(STWUX GPRC:$rS, ptr_rc_nor0:$ptrreg, ptr_rc:$ptroff)>;
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def : Pat<(pre_store F4RC:$rS, ptr_rc_nor0:$ptrreg, ptr_rc:$ptroff),
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(STFSUX F4RC:$rS, ptr_rc_nor0:$ptrreg, ptr_rc:$ptroff)>;
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def : Pat<(pre_store F8RC:$rS, ptr_rc_nor0:$ptrreg, ptr_rc:$ptroff),
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(STFDUX F8RC:$rS, ptr_rc_nor0:$ptrreg, ptr_rc:$ptroff)>;
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def : Pat<(pre_truncsti8 i32:$rS, iPTR:$ptrreg, iPTR:$ptroff),
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(STBUX $rS, $ptrreg, $ptroff)>;
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def : Pat<(pre_truncsti16 i32:$rS, iPTR:$ptrreg, iPTR:$ptroff),
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(STHUX $rS, $ptrreg, $ptroff)>;
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def : Pat<(pre_store i32:$rS, iPTR:$ptrreg, iPTR:$ptroff),
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(STWUX $rS, $ptrreg, $ptroff)>;
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def : Pat<(pre_store f32:$rS, iPTR:$ptrreg, iPTR:$ptroff),
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(STFSUX $rS, $ptrreg, $ptroff)>;
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def : Pat<(pre_store f64:$rS, iPTR:$ptrreg, iPTR:$ptroff),
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(STFDUX $rS, $ptrreg, $ptroff)>;
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def SYNC : XForm_24_sync<31, 598, (outs), (ins),
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"sync", LdStSync,
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@ -1530,37 +1530,37 @@ def : Pat<(i32 imm:$imm),
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(ORI (LIS (HI16 imm:$imm)), (LO16 imm:$imm))>;
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// Implement the 'not' operation with the NOR instruction.
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def NOT : Pat<(not GPRC:$in),
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(NOR GPRC:$in, GPRC:$in)>;
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def NOT : Pat<(not i32:$in),
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(NOR $in, $in)>;
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// ADD an arbitrary immediate.
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def : Pat<(add GPRC:$in, imm:$imm),
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(ADDIS (ADDI GPRC:$in, (LO16 imm:$imm)), (HA16 imm:$imm))>;
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def : Pat<(add i32:$in, imm:$imm),
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(ADDIS (ADDI $in, (LO16 imm:$imm)), (HA16 imm:$imm))>;
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// OR an arbitrary immediate.
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def : Pat<(or GPRC:$in, imm:$imm),
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(ORIS (ORI GPRC:$in, (LO16 imm:$imm)), (HI16 imm:$imm))>;
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def : Pat<(or i32:$in, imm:$imm),
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(ORIS (ORI $in, (LO16 imm:$imm)), (HI16 imm:$imm))>;
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// XOR an arbitrary immediate.
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def : Pat<(xor GPRC:$in, imm:$imm),
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(XORIS (XORI GPRC:$in, (LO16 imm:$imm)), (HI16 imm:$imm))>;
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def : Pat<(xor i32:$in, imm:$imm),
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(XORIS (XORI $in, (LO16 imm:$imm)), (HI16 imm:$imm))>;
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// SUBFIC
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def : Pat<(sub immSExt16:$imm, GPRC:$in),
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(SUBFIC GPRC:$in, imm:$imm)>;
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def : Pat<(sub immSExt16:$imm, i32:$in),
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(SUBFIC $in, imm:$imm)>;
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// SHL/SRL
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def : Pat<(shl GPRC:$in, (i32 imm:$imm)),
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(RLWINM GPRC:$in, imm:$imm, 0, (SHL32 imm:$imm))>;
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def : Pat<(srl GPRC:$in, (i32 imm:$imm)),
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(RLWINM GPRC:$in, (SRL32 imm:$imm), imm:$imm, 31)>;
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def : Pat<(shl i32:$in, (i32 imm:$imm)),
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(RLWINM $in, imm:$imm, 0, (SHL32 imm:$imm))>;
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def : Pat<(srl i32:$in, (i32 imm:$imm)),
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(RLWINM $in, (SRL32 imm:$imm), imm:$imm, 31)>;
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// ROTL
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def : Pat<(rotl GPRC:$in, GPRC:$sh),
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(RLWNM GPRC:$in, GPRC:$sh, 0, 31)>;
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def : Pat<(rotl GPRC:$in, (i32 imm:$imm)),
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(RLWINM GPRC:$in, imm:$imm, 0, 31)>;
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def : Pat<(rotl i32:$in, i32:$sh),
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(RLWNM $in, $sh, 0, 31)>;
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def : Pat<(rotl i32:$in, (i32 imm:$imm)),
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(RLWINM $in, imm:$imm, 0, 31)>;
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// RLWNM
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def : Pat<(and (rotl GPRC:$in, GPRC:$sh), maskimm32:$imm),
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(RLWNM GPRC:$in, GPRC:$sh, (MB maskimm32:$imm), (ME maskimm32:$imm))>;
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def : Pat<(and (rotl i32:$in, i32:$sh), maskimm32:$imm),
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(RLWNM $in, $sh, (MB maskimm32:$imm), (ME maskimm32:$imm))>;
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// Calls
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def : Pat<(PPCcall (i32 tglobaladdr:$dst)),
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@ -1589,28 +1589,28 @@ def : Pat<(PPChi tjumptable:$in, 0), (LIS tjumptable:$in)>;
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def : Pat<(PPClo tjumptable:$in, 0), (LI tjumptable:$in)>;
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def : Pat<(PPChi tblockaddress:$in, 0), (LIS tblockaddress:$in)>;
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def : Pat<(PPClo tblockaddress:$in, 0), (LI tblockaddress:$in)>;
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def : Pat<(PPChi tglobaltlsaddr:$g, GPRC:$in),
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(ADDIS GPRC:$in, tglobaltlsaddr:$g)>;
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def : Pat<(PPClo tglobaltlsaddr:$g, GPRC:$in),
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(ADDIL GPRC:$in, tglobaltlsaddr:$g)>;
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def : Pat<(add GPRC:$in, (PPChi tglobaladdr:$g, 0)),
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(ADDIS GPRC:$in, tglobaladdr:$g)>;
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def : Pat<(add GPRC:$in, (PPChi tconstpool:$g, 0)),
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(ADDIS GPRC:$in, tconstpool:$g)>;
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def : Pat<(add GPRC:$in, (PPChi tjumptable:$g, 0)),
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(ADDIS GPRC:$in, tjumptable:$g)>;
|
||||
def : Pat<(add GPRC:$in, (PPChi tblockaddress:$g, 0)),
|
||||
(ADDIS GPRC:$in, tblockaddress:$g)>;
|
||||
def : Pat<(PPChi tglobaltlsaddr:$g, i32:$in),
|
||||
(ADDIS $in, tglobaltlsaddr:$g)>;
|
||||
def : Pat<(PPClo tglobaltlsaddr:$g, i32:$in),
|
||||
(ADDIL $in, tglobaltlsaddr:$g)>;
|
||||
def : Pat<(add i32:$in, (PPChi tglobaladdr:$g, 0)),
|
||||
(ADDIS $in, tglobaladdr:$g)>;
|
||||
def : Pat<(add i32:$in, (PPChi tconstpool:$g, 0)),
|
||||
(ADDIS $in, tconstpool:$g)>;
|
||||
def : Pat<(add i32:$in, (PPChi tjumptable:$g, 0)),
|
||||
(ADDIS $in, tjumptable:$g)>;
|
||||
def : Pat<(add i32:$in, (PPChi tblockaddress:$g, 0)),
|
||||
(ADDIS $in, tblockaddress:$g)>;
|
||||
|
||||
// Standard shifts. These are represented separately from the real shifts above
|
||||
// so that we can distinguish between shifts that allow 5-bit and 6-bit shift
|
||||
// amounts.
|
||||
def : Pat<(sra GPRC:$rS, GPRC:$rB),
|
||||
(SRAW GPRC:$rS, GPRC:$rB)>;
|
||||
def : Pat<(srl GPRC:$rS, GPRC:$rB),
|
||||
(SRW GPRC:$rS, GPRC:$rB)>;
|
||||
def : Pat<(shl GPRC:$rS, GPRC:$rB),
|
||||
(SLW GPRC:$rS, GPRC:$rB)>;
|
||||
def : Pat<(sra i32:$rS, i32:$rB),
|
||||
(SRAW $rS, $rB)>;
|
||||
def : Pat<(srl i32:$rS, i32:$rB),
|
||||
(SRW $rS, $rB)>;
|
||||
def : Pat<(shl i32:$rS, i32:$rB),
|
||||
(SLW $rS, $rB)>;
|
||||
|
||||
def : Pat<(zextloadi1 iaddr:$src),
|
||||
(LBZ iaddr:$src)>;
|
||||
@ -1633,8 +1633,8 @@ def : Pat<(f64 (extloadf32 iaddr:$src)),
|
||||
def : Pat<(f64 (extloadf32 xaddr:$src)),
|
||||
(COPY_TO_REGCLASS (LFSX xaddr:$src), F8RC)>;
|
||||
|
||||
def : Pat<(f64 (fextend F4RC:$src)),
|
||||
(COPY_TO_REGCLASS F4RC:$src, F8RC)>;
|
||||
def : Pat<(f64 (fextend f32:$src)),
|
||||
(COPY_TO_REGCLASS $src, F8RC)>;
|
||||
|
||||
// Memory barriers
|
||||
def : Pat<(membarrier (i32 imm /*ll*/),
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user