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Simplify max/minp[s|d] dagcombine matching

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140199 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bruno Cardoso Lopes 2011-09-20 22:34:45 +00:00
parent e3039de722
commit 149f29f1fd
1 changed files with 3 additions and 6 deletions
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9
lib/Target/X86/X86ISelLowering.cpp
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@ -12562,17 +12562,14 @@ static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
// Get the LHS/RHS of the select.
SDValue LHS = N->getOperand(1);
SDValue RHS = N->getOperand(2);
EVT VT = LHS.getValueType();
// If we have SSE[12] support, try to form min/max nodes. SSE min/max
// instructions match the semantics of the common C idiom x<y?x:y but not
// x<=y?x:y, because of how they handle negative zero (which can be
// ignored in unsafe-math mode).
if (Cond.getOpcode() == ISD::SETCC &&
((Subtarget->hasXMMInt() &&
(LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::v4f32 ||
LHS.getValueType() == MVT::f64 || LHS.getValueType() == MVT::v2f64)) ||
(Subtarget->hasAVX() &&
(LHS.getValueType() == MVT::v8f32 || LHS.getValueType() == MVT::v4f64)))) {
if (Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() &&
VT != MVT::f80 && DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
unsigned Opcode = 0;