6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-02-06 06:33:24 +00:00
Code Issues Projects Releases Wiki Activity

LDCL_POST and STCL_POST need one's-complement offsets, rather than two's complement offsets. Add an appropriate immediate type for them.

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136896 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Owen Anderson 2011-08-04 18:24:14 +00:00
parent 5c4e52e496
commit 154c41dbbc
4 changed files with 24 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

13
lib/Target/ARM/ARMInstrInfo.td
View File

@ -626,6 +626,17 @@ def postidx_imm8 : Operand<i32> {
let MIOperandInfo = (ops i32imm); let MIOperandInfo = (ops i32imm);
} }
// postidx_imm8s4 := +/- [0,1020]
//
// 9 bit value:
// {8} 1 is imm8 is non-negative. 0 otherwise.
// {7-0} [0,255] imm8 value, scaled by 4.
def postidx_imm8s4 : Operand<i32> {
let PrintMethod = "printPostIdxImm8s4Operand";
let MIOperandInfo = (ops i32imm);
}
// postidx_reg := +/- reg // postidx_reg := +/- reg
// //
def PostIdxRegAsmOperand : AsmOperandClass { def PostIdxRegAsmOperand : AsmOperandClass {
@ -3974,7 +3985,7 @@ multiclass LdStCop<bits<4> op31_28, bit load, dag ops, string opc, string cond>{
def L_POST : ACI<(outs), def L_POST : ACI<(outs),
!con((ins nohash_imm:$cop, nohash_imm:$CRd, addr_offset_none:$addr, !con((ins nohash_imm:$cop, nohash_imm:$CRd, addr_offset_none:$addr,
i32imm:$offset), ops), postidx_imm8s4:$offset), ops),
!strconcat(!strconcat(opc, "l"), cond), "\tp$cop, cr$CRd, $addr, $offset", !strconcat(!strconcat(opc, "l"), cond), "\tp$cop, cr$CRd, $addr, $offset",
IndexModePost> { IndexModePost> {
let Inst{31-28} = op31_28; let Inst{31-28} = op31_28;

9
lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
View File

@ -382,6 +382,15 @@ void ARMInstPrinter::printPostIdxImm8Operand(const MCInst *MI,
O << '#' << ((Imm & 256) ? "" : "-") << (Imm & 0xff); O << '#' << ((Imm & 256) ? "" : "-") << (Imm & 0xff);
} }
void ARMInstPrinter::printPostIdxImm8s4Operand(const MCInst *MI,
unsigned OpNum,
raw_ostream &O) {
const MCOperand &MO = MI->getOperand(OpNum);
unsigned Imm = MO.getImm();
O << '#' << ((Imm & 256) ? "" : "-") << ((Imm & 0xff) << 2);
}
void ARMInstPrinter::printLdStmModeOperand(const MCInst *MI, unsigned OpNum, void ARMInstPrinter::printLdStmModeOperand(const MCInst *MI, unsigned OpNum,
raw_ostream &O) { raw_ostream &O) {
ARM_AM::AMSubMode Mode = ARM_AM::getAM4SubMode(MI->getOperand(OpNum) ARM_AM::AMSubMode Mode = ARM_AM::getAM4SubMode(MI->getOperand(OpNum)

2
lib/Target/ARM/InstPrinter/ARMInstPrinter.h
View File

@ -55,6 +55,8 @@ public:
void printAM3PreOrOffsetIndexOp(const MCInst *MI, unsigned Op,raw_ostream &O); void printAM3PreOrOffsetIndexOp(const MCInst *MI, unsigned Op,raw_ostream &O);
void printPostIdxImm8Operand(const MCInst *MI, unsigned OpNum, void printPostIdxImm8Operand(const MCInst *MI, unsigned OpNum,
raw_ostream &O); raw_ostream &O);
void printPostIdxImm8s4Operand(const MCInst *MI, unsigned OpNum,
raw_ostream &O);
void printLdStmModeOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O); void printLdStmModeOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
void printAddrMode5Operand(const MCInst *MI, unsigned OpNum, raw_ostream &O); void printAddrMode5Operand(const MCInst *MI, unsigned OpNum, raw_ostream &O);

1
utils/TableGen/EDEmitter.cpp
View File

@ -614,6 +614,7 @@ static int ARMFlagFromOpName(LiteralConstantEmitter *type,
IMM("shr_imm64"); IMM("shr_imm64");
IMM("t2ldrlabel"); IMM("t2ldrlabel");
IMM("postidx_imm8"); IMM("postidx_imm8");
IMM("postidx_imm8s4");
MISC("brtarget", "kOperandTypeARMBranchTarget"); // ? MISC("brtarget", "kOperandTypeARMBranchTarget"); // ?
MISC("uncondbrtarget", "kOperandTypeARMBranchTarget"); // ? MISC("uncondbrtarget", "kOperandTypeARMBranchTarget"); // ?