6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-11-01 15:11:24 +00:00
Code Issues Projects Releases Wiki Activity

More refactoring. Move getRegClass from TargetOperandInfo to TargetInstrInfo.

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133944 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng 2011-06-27 21:26:13 +00:00
parent bea6f615ee
commit 15993f83a4
18 changed files with 54 additions and 63 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

15
include/llvm/Target/TargetInstrDesc.h
View File

@ -52,9 +52,6 @@ public:
/// if the operand is a register. If isLookupPtrRegClass is set, then this is
/// an index that is passed to TargetRegisterInfo::getPointerRegClass(x) to
/// get a dynamic register class.
///
/// NOTE: This member should be considered to be private, all access should go
/// through "getRegClass(TRI)" below.
short RegClass;
/// Flags - These are flags from the TOI::OperandFlags enum.
@ -65,12 +62,6 @@ public:
unsigned Constraints;
/// Currently no other information.
/// getRegClass - Get the register class for the operand, handling resolution
/// of "symbolic" pointer register classes etc. If this is not a register
/// operand, this returns null.
const TargetRegisterClass *getRegClass(const TargetRegisterInfo *TRI) const;
/// isLookupPtrRegClass - Set if this operand is a pointer value and it
/// requires a callback to look up its register class.
bool isLookupPtrRegClass() const { return Flags&(1 <<TOI::LookupPtrRegClass);}
@ -154,12 +145,6 @@ public:
return -1;
}
/// getRegClass - Returns the register class constraint for OpNum, or NULL.
const TargetRegisterClass *getRegClass(unsigned OpNum,
const TargetRegisterInfo *TRI) const {
return OpNum < NumOperands ? OpInfo[OpNum].getRegClass(TRI) : 0;
}
/// getOpcode - Return the opcode number for this descriptor.
unsigned getOpcode() const {
return Opcode;

6
include/llvm/Target/TargetInstrInfo.h
View File

@ -60,6 +60,12 @@ public:
return Descriptors[Opcode];
}
/// getRegClass - Givem a machine instruction descriptor, returns the register
/// class constraint for OpNum, or NULL.
const TargetRegisterClass *getRegClass(const TargetInstrDesc &TID,
unsigned OpNum,
const TargetRegisterInfo *TRI) const;
/// isTriviallyReMaterializable - Return true if the instruction is trivially
/// rematerializable, meaning it has no side effects and requires no operands
/// that aren't always available.

4
lib/CodeGen/AggressiveAntiDepBreaker.cpp
View File

@ -404,7 +404,7 @@ void AggressiveAntiDepBreaker::PrescanInstruction(MachineInstr *MI,
// Note register reference...
const TargetRegisterClass *RC = NULL;
if (i < MI->getDesc().getNumOperands())
RC = MI->getDesc().OpInfo[i].getRegClass(TRI);
RC = TII->getRegClass(MI->getDesc(), i, TRI);
AggressiveAntiDepState::RegisterReference RR = { &MO, RC };
RegRefs.insert(std::make_pair(Reg, RR));
}
@ -479,7 +479,7 @@ void AggressiveAntiDepBreaker::ScanInstruction(MachineInstr *MI,
// Note register reference...
const TargetRegisterClass *RC = NULL;
if (i < MI->getDesc().getNumOperands())
RC = MI->getDesc().OpInfo[i].getRegClass(TRI);
RC = TII->getRegClass(MI->getDesc(), i, TRI);
AggressiveAntiDepState::RegisterReference RR = { &MO, RC };
RegRefs.insert(std::make_pair(Reg, RR));
}

3
lib/CodeGen/CalcSpillWeights.cpp
View File

@ -188,6 +188,7 @@ void VirtRegAuxInfo::CalculateWeightAndHint(LiveInterval &li) {
void VirtRegAuxInfo::CalculateRegClass(unsigned reg) {
MachineRegisterInfo &MRI = MF.getRegInfo();
const TargetInstrInfo *TII = MF.getTarget().getInstrInfo();
const TargetRegisterInfo *TRI = MF.getTarget().getRegisterInfo();
const TargetRegisterClass *OldRC = MRI.getRegClass(reg);
const TargetRegisterClass *NewRC = TRI->getLargestLegalSuperClass(OldRC);
@ -203,7 +204,7 @@ void VirtRegAuxInfo::CalculateRegClass(unsigned reg) {
if (I.getOperand().getSubReg())
return;
const TargetRegisterClass *OpRC =
I->getDesc().getRegClass(I.getOperandNo(), TRI);
TII->getRegClass(I->getDesc(), I.getOperandNo(), TRI);
if (OpRC)
NewRC = getCommonSubClass(NewRC, OpRC);
if (!NewRC || NewRC == OldRC)

4
lib/CodeGen/CriticalAntiDepBreaker.cpp
View File

@ -207,7 +207,7 @@ void CriticalAntiDepBreaker::PrescanInstruction(MachineInstr *MI) {
const TargetRegisterClass *NewRC = 0;
if (i < MI->getDesc().getNumOperands())
NewRC = MI->getDesc().OpInfo[i].getRegClass(TRI);
NewRC = TII->getRegClass(MI->getDesc(), i, TRI);
// For now, only allow the register to be changed if its register
// class is consistent across all uses.
@ -295,7 +295,7 @@ void CriticalAntiDepBreaker::ScanInstruction(MachineInstr *MI,
const TargetRegisterClass *NewRC = 0;
if (i < MI->getDesc().getNumOperands())
NewRC = MI->getDesc().OpInfo[i].getRegClass(TRI);
NewRC = TII->getRegClass(MI->getDesc(), i, TRI);
// For now, only allow the register to be changed if its register
// class is consistent across all uses.

2
lib/CodeGen/MachineLICM.cpp
View File

@ -1020,7 +1020,7 @@ MachineInstr *MachineLICM::ExtractHoistableLoad(MachineInstr *MI) {
if (NewOpc == 0) return 0;
const TargetInstrDesc &TID = TII->get(NewOpc);
if (TID.getNumDefs() != 1) return 0;
const TargetRegisterClass *RC = TID.OpInfo[LoadRegIndex].getRegClass(TRI);
const TargetRegisterClass *RC = TII->getRegClass(TID, LoadRegIndex, TRI);
// Ok, we're unfolding. Create a temporary register and do the unfold.
unsigned Reg = MRI->createVirtualRegister(RC);

8
lib/CodeGen/MachineVerifier.cpp
View File

@ -62,6 +62,7 @@ namespace {
raw_ostream *OS;
const MachineFunction *MF;
const TargetMachine *TM;
const TargetInstrInfo *TII;
const TargetRegisterInfo *TRI;
const MachineRegisterInfo *MRI;
@ -255,6 +256,7 @@ bool MachineVerifier::runOnMachineFunction(MachineFunction &MF) {
this->MF = &MF;
TM = &MF.getTarget();
TII = TM->getInstrInfo();
TRI = TM->getRegisterInfo();
MRI = &MF.getRegInfo();
@ -387,8 +389,6 @@ static bool matchPair(MachineBasicBlock::const_succ_iterator i,
void
MachineVerifier::visitMachineBasicBlockBefore(const MachineBasicBlock *MBB) {
const TargetInstrInfo *TII = MF->getTarget().getInstrInfo();
// Count the number of landing pad successors.
SmallPtrSet<MachineBasicBlock*, 4> LandingPadSuccs;
for (MachineBasicBlock::const_succ_iterator I = MBB->succ_begin(),
@ -723,7 +723,7 @@ MachineVerifier::visitMachineOperand(const MachineOperand *MO, unsigned MONum) {
}
sr = s;
}
if (const TargetRegisterClass *DRC = TOI.getRegClass(TRI)) {
if (const TargetRegisterClass *DRC = TII->getRegClass(TI, MONum, TRI)) {
if (!DRC->contains(sr)) {
report("Illegal physical register for instruction", MO, MONum);
*OS << TRI->getName(sr) << " is not a "
@ -743,7 +743,7 @@ MachineVerifier::visitMachineOperand(const MachineOperand *MO, unsigned MONum) {
}
RC = SRC;
}
if (const TargetRegisterClass *DRC = TOI.getRegClass(TRI)) {
if (const TargetRegisterClass *DRC = TII->getRegClass(TI, MONum, TRI)) {
if (!RC->hasSuperClassEq(DRC)) {
report("Illegal virtual register for instruction", MO, MONum);
*OS << "Expected a " << DRC->getName() << " register, but got a "

4
lib/CodeGen/RegisterCoalescer.cpp
View File

@ -701,7 +701,7 @@ bool RegisterCoalescer::ReMaterializeTrivialDef(LiveInterval &SrcInt,
// Make sure the copy destination register class fits the instruction
// definition register class. The mismatch can happen as a result of earlier
// extract_subreg, insert_subreg, subreg_to_reg coalescing.
const TargetRegisterClass *RC = TID.OpInfo[0].getRegClass(tri_);
const TargetRegisterClass *RC = tii_->getRegClass(TID, 0, tri_);
if (TargetRegisterInfo::isVirtualRegister(DstReg)) {
if (mri_->getRegClass(DstReg) != RC)
return false;
@ -718,7 +718,7 @@ bool RegisterCoalescer::ReMaterializeTrivialDef(LiveInterval &SrcInt,
const TargetRegisterClass *DstRC = mri_->getRegClass(DstReg);
const TargetRegisterClass *DstSubRC =
DstRC->getSubRegisterRegClass(DstSubIdx);
const TargetRegisterClass *DefRC = TID.OpInfo[0].getRegClass(tri_);
const TargetRegisterClass *DefRC = tii_->getRegClass(TID, 0, tri_);
if (DefRC == DstRC)
DstSubIdx = 0;
else if (DefRC != DstSubRC)

6
lib/CodeGen/SelectionDAG/InstrEmitter.cpp
View File

@ -109,7 +109,7 @@ EmitCopyFromReg(SDNode *Node, unsigned ResNo, bool IsClone, bool IsCloned,
const TargetInstrDesc &II = TII->get(User->getMachineOpcode());
const TargetRegisterClass *RC = 0;
if (i+II.getNumDefs() < II.getNumOperands())
RC = II.OpInfo[i+II.getNumDefs()].getRegClass(TRI);
RC = TII->getRegClass(II, i+II.getNumDefs(), TRI);
if (!UseRC)
UseRC = RC;
else if (RC) {
@ -189,7 +189,7 @@ void InstrEmitter::CreateVirtualRegisters(SDNode *Node, MachineInstr *MI,
// is a vreg in the same register class, use the CopyToReg'd destination
// register instead of creating a new vreg.
unsigned VRBase = 0;
const TargetRegisterClass *RC = II.OpInfo[i].getRegClass(TRI);
const TargetRegisterClass *RC = TII->getRegClass(II, i, TRI);
if (II.OpInfo[i].isOptionalDef()) {
// Optional def must be a physical register.
unsigned NumResults = CountResults(Node);
@ -285,7 +285,7 @@ InstrEmitter::AddRegisterOperand(MachineInstr *MI, SDValue Op,
const TargetRegisterClass *SrcRC = MRI->getRegClass(VReg);
const TargetRegisterClass *DstRC = 0;
if (IIOpNum < II->getNumOperands())
DstRC = II->OpInfo[IIOpNum].getRegClass(TRI);
DstRC = TII->getRegClass(*II, IIOpNum, TRI);
assert((DstRC || (TID.isVariadic() && IIOpNum >= TID.getNumOperands())) &&
"Don't have operand info for this instruction!");
if (DstRC && !SrcRC->hasSuperClassEq(DstRC)) {

2
lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
View File

@ -303,7 +303,7 @@ static void GetCostForDef(const ScheduleDAGSDNodes::RegDefIter &RegDefPos,
unsigned Idx = RegDefPos.GetIdx();
const TargetInstrDesc Desc = TII->get(Opcode);
const TargetRegisterClass *RC = Desc.getRegClass(Idx, TRI);
const TargetRegisterClass *RC = TII->getRegClass(Desc, Idx, TRI);
RegClass = RC->getID();
// FIXME: Cost arbitrarily set to 1 because there doesn't seem to be a
// better way to determine it.

4
lib/CodeGen/StackSlotColoring.cpp
View File

@ -521,7 +521,7 @@ bool StackSlotColoring::PropagateBackward(MachineBasicBlock::iterator MII,
if (MO.getSubReg() || MII->isSubregToReg())
return false;
const TargetRegisterClass *RC = TID.OpInfo[i].getRegClass(TRI);
const TargetRegisterClass *RC = TII->getRegClass(TID, i, TRI);
if (RC && !RC->contains(NewReg))
return false;
@ -583,7 +583,7 @@ bool StackSlotColoring::PropagateForward(MachineBasicBlock::iterator MII,
if (MO.getSubReg())
return false;
const TargetRegisterClass *RC = TID.OpInfo[i].getRegClass(TRI);
const TargetRegisterClass *RC = TII->getRegClass(TID, i, TRI);
if (RC && !RC->contains(NewReg))
return false;
if (MO.isKill())

2
lib/CodeGen/TwoAddressInstructionPass.cpp
View File

@ -943,7 +943,7 @@ TryInstructionTransform(MachineBasicBlock::iterator &mi,
// Unfold the load.
DEBUG(dbgs() << "2addr: UNFOLDING: " << *mi);
const TargetRegisterClass *RC =
UnfoldTID.OpInfo[LoadRegIndex].getRegClass(TRI);
TII->getRegClass(UnfoldTID, LoadRegIndex, TRI);
unsigned Reg = MRI->createVirtualRegister(RC);
SmallVector<MachineInstr *, 2> NewMIs;
if (!TII->unfoldMemoryOperand(MF, mi, Reg,

2
lib/Target/ARM/ARMBaseRegisterInfo.cpp
View File

@ -1112,7 +1112,7 @@ materializeFrameBaseRegister(MachineBasicBlock *MBB,
const TargetInstrDesc &TID = TII.get(ADDriOpc);
MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
MRI.constrainRegClass(BaseReg, TID.OpInfo[0].getRegClass(this));
MRI.constrainRegClass(BaseReg, TII.getRegClass(TID, 0, this));
MachineInstrBuilder MIB = BuildMI(*MBB, Ins, DL, TID, BaseReg)
.addFrameIndex(FrameIdx).addImm(Offset);

2
lib/Target/ARM/ARMLoadStoreOptimizer.cpp
View File

@ -1673,7 +1673,7 @@ bool ARMPreAllocLoadStoreOpt::RescheduleOps(MachineBasicBlock *MBB,
Ops.pop_back();
const TargetInstrDesc &TID = TII->get(NewOpc);
const TargetRegisterClass *TRC = TID.OpInfo[0].getRegClass(TRI);
const TargetRegisterClass *TRC = TII->getRegClass(TID, 0, TRI);
MRI->constrainRegClass(EvenReg, TRC);
MRI->constrainRegClass(OddReg, TRC);

2
lib/Target/ARM/MLxExpansionPass.cpp
View File

@ -220,7 +220,7 @@ MLxExpansion::ExpandFPMLxInstruction(MachineBasicBlock &MBB, MachineInstr *MI,
const TargetInstrDesc &TID1 = TII->get(MulOpc);
const TargetInstrDesc &TID2 = TII->get(AddSubOpc);
unsigned TmpReg = MRI->createVirtualRegister(TID1.getRegClass(0, TRI));
unsigned TmpReg = MRI->createVirtualRegister(TII->getRegClass(TID1, 0, TRI));
MachineInstrBuilder MIB = BuildMI(MBB, *MI, MI->getDebugLoc(), TID1, TmpReg)
.addReg(Src1Reg, getKillRegState(Src1Kill))

4
lib/Target/Blackfin/BlackfinISelDAGToDAG.cpp
View File

@ -154,13 +154,13 @@ void BlackfinDAGToDAGISel::FixRegisterClasses(SelectionDAG &DAG) {
if (UI.getUse().getResNo() >= DefTID.getNumDefs())
continue;
const TargetRegisterClass *DefRC =
DefTID.OpInfo[UI.getUse().getResNo()].getRegClass(TRI);
TII.getRegClass(DefTID, UI.getUse().getResNo(), TRI);
const TargetInstrDesc &UseTID = TII.get(UI->getMachineOpcode());
if (UseTID.getNumDefs()+UI.getOperandNo() >= UseTID.getNumOperands())
continue;
const TargetRegisterClass *UseRC =
UseTID.OpInfo[UseTID.getNumDefs()+UI.getOperandNo()].getRegClass(TRI);
TII.getRegClass(UseTID, UseTID.getNumDefs()+UI.getOperandNo(), TRI);
if (!DefRC || !UseRC)
continue;
// We cannot copy CC <-> !(CC/D)

36
lib/Target/TargetInstrInfo.cpp
View File

@ -20,24 +20,6 @@
#include <cctype>
using namespace llvm;
//===----------------------------------------------------------------------===//
// TargetOperandInfo
//===----------------------------------------------------------------------===//
/// getRegClass - Get the register class for the operand, handling resolution
/// of "symbolic" pointer register classes etc. If this is not a register
/// operand, this returns null.
const TargetRegisterClass *
TargetOperandInfo::getRegClass(const TargetRegisterInfo *TRI) const {
if (isLookupPtrRegClass())
return TRI->getPointerRegClass(RegClass);
// Instructions like INSERT_SUBREG do not have fixed register classes.
if (RegClass < 0)
return 0;
// Otherwise just look it up normally.
return TRI->getRegClass(RegClass);
}
//===----------------------------------------------------------------------===//
// TargetInstrInfo
//===----------------------------------------------------------------------===//
@ -50,6 +32,24 @@ TargetInstrInfo::TargetInstrInfo(const TargetInstrDesc* Desc,
TargetInstrInfo::~TargetInstrInfo() {
}
const TargetRegisterClass*
TargetInstrInfo::getRegClass(const TargetInstrDesc &TID, unsigned OpNum,
const TargetRegisterInfo *TRI) const {
if (OpNum >= TID.getNumOperands())
return 0;
short RegClass = TID.OpInfo[OpNum].RegClass;
if (TID.OpInfo[OpNum].isLookupPtrRegClass())
return TRI->getPointerRegClass(RegClass);
// Instructions like INSERT_SUBREG do not have fixed register classes.
if (RegClass < 0)
return 0;
// Otherwise just look it up normally.
return TRI->getRegClass(RegClass);
}
unsigned
TargetInstrInfo::getNumMicroOps(const InstrItineraryData *ItinData,
const MachineInstr *MI) const {

11
lib/Target/X86/X86InstrInfo.cpp
View File

@ -2274,7 +2274,7 @@ X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
return NULL;
bool NarrowToMOV32rm = false;
if (Size) {
unsigned RCSize = MI->getDesc().OpInfo[i].getRegClass(&RI)->getSize();
unsigned RCSize = getRegClass(MI->getDesc(), i, &RI)->getSize();
if (Size < RCSize) {
// Check if it's safe to fold the load. If the size of the object is
// narrower than the load width, then it's not.
@ -2590,8 +2590,7 @@ bool X86InstrInfo::unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI,
UnfoldStore &= FoldedStore;
const TargetInstrDesc &TID = get(Opc);
const TargetOperandInfo &TOI = TID.OpInfo[Index];
const TargetRegisterClass *RC = TOI.getRegClass(&RI);
const TargetRegisterClass *RC = getRegClass(TID, Index, &RI);
if (!MI->hasOneMemOperand() &&
RC == &X86::VR128RegClass &&
!TM.getSubtarget<X86Subtarget>().isUnalignedMemAccessFast())
@ -2686,7 +2685,7 @@ bool X86InstrInfo::unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI,
// Emit the store instruction.
if (UnfoldStore) {
const TargetRegisterClass *DstRC = TID.OpInfo[0].getRegClass(&RI);
const TargetRegisterClass *DstRC = getRegClass(TID, 0, &RI);
std::pair<MachineInstr::mmo_iterator,
MachineInstr::mmo_iterator> MMOs =
MF.extractStoreMemRefs(MI->memoperands_begin(),
@ -2712,7 +2711,7 @@ X86InstrInfo::unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
bool FoldedLoad = I->second.second & (1 << 4);
bool FoldedStore = I->second.second & (1 << 5);
const TargetInstrDesc &TID = get(Opc);
const TargetRegisterClass *RC = TID.OpInfo[Index].getRegClass(&RI);
const TargetRegisterClass *RC = getRegClass(TID, Index, &RI);
unsigned NumDefs = TID.NumDefs;
std::vector<SDValue> AddrOps;
std::vector<SDValue> BeforeOps;
@ -2758,7 +2757,7 @@ X86InstrInfo::unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
std::vector<EVT> VTs;
const TargetRegisterClass *DstRC = 0;
if (TID.getNumDefs() > 0) {
DstRC = TID.OpInfo[0].getRegClass(&RI);
DstRC = getRegClass(TID, 0, &RI);
VTs.push_back(*DstRC->vt_begin());
}
for (unsigned i = 0, e = N->getNumValues(); i != e; ++i) {