6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-01-16 14:31:59 +00:00
Code Issues Projects Releases Wiki Activity

* Do not allocate r0 as we use it indiscriminantly in the instr selector.

Browse Source 
* Do not define CR register class because we don't (yet) have the i4 type


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14551 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Misha Brukman 2004-07-01 21:24:50 +00:00
parent 4363bdb0e5
commit 15eb0a15e5
1 changed files with 4 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
lib/Target/PowerPC/PPCRegisterInfo.td
View File

@ -75,12 +75,12 @@ def TBU : SPR<5>;
/// Register classes
def GPRC :
RegisterClass<i32, 4,
[R0, R11, R12, R13, R14, R15, R16, R17, R18, R19, R20, R21, R22, R23, R24,
R25, R26, R27, R28, R29, R30, R31, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10]>
[R11, R12, R13, R14, R15, R16, R17, R18, R19, R20, R21, R22, R23, R24, R25,
R26, R27, R28, R29, R30, R31, R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10]>
{
let Methods = [{
iterator allocation_order_end(MachineFunction &MF) const {
return end()-9; // do not allocate r1-r10
return end()-10; // do not allocate r0-r10
}
}];
}
@ -89,4 +89,4 @@ def FPRC : RegisterClass<f64, 8, [F0, F1, F2, F3, F4, F5, F6, F7,
F8, F9, F10, F11, F12, F13, F14, F15, F16, F17, F18, F19, F20, F21,
F22, F23, F24, F25, F26, F27, F28, F29, F30, F31]>;
def CRRC : RegisterClass<i4, 4, [CR0, CR1, CR2, CR3, CR4, CR5, CR6, CR7]>;
//def CRRC : RegisterClass<i4, 1, [CR0, CR1, CR2, CR3, CR4, CR5, CR6, CR7]>;