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Make sure to expand SIGN_EXTEND_INREG for NEON vectors. PR11319, round 3.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144361 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Eli Friedman 2011-11-11 03:16:38 +00:00
parent d61c34ba30
commit 15f58c56e9
2 changed files with 10 additions and 0 deletions
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1
lib/Target/ARM/ARMISelLowering.cpp
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@ -127,6 +127,7 @@ void ARMTargetLowering::addTypeForNEON(EVT VT, EVT PromotedLdStVT,
setOperationAction(ISD::EXTRACT_SUBVECTOR, VT.getSimpleVT(), Legal);
setOperationAction(ISD::SELECT, VT.getSimpleVT(), Expand);
setOperationAction(ISD::SELECT_CC, VT.getSimpleVT(), Expand);
setOperationAction(ISD::SIGN_EXTEND_INREG, VT.getSimpleVT(), Expand);
if (VT.isInteger()) {
setOperationAction(ISD::SHL, VT.getSimpleVT(), Custom);
setOperationAction(ISD::SRA, VT.getSimpleVT(), Custom);

9
test/CodeGen/ARM/2011-11-07-PromoteVectorLoadStore.ll
View File

@ -13,3 +13,12 @@ define void @test_neon_vector_add_2xi8() nounwind {
store <2 x i8> %3, <2 x i8>* @i8_res
ret void
}
define void @test_neon_ld_st_volatile_with_ashr_2xi8() {
; CHECK: test_neon_ld_st_volatile_with_ashr_2xi8:
%1 = load volatile <2 x i8>* @i8_src1
%2 = load volatile <2 x i8>* @i8_src2
%3 = ashr <2 x i8> %1, %2
store volatile <2 x i8> %3, <2 x i8>* @i8_res
ret void
}