mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2025-04-06 09:44:39 +00:00
Split out the PPC instruction class IntSimple from IntGeneral.
On the POWER7, adds and logical operations can also be handled in the load/store pipelines. We'll call these IntSimple. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158366 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Hal Finkel
parent
b9c592f4c5
commit
16803097fb
@ -288,36 +288,36 @@ def MFLR8 : XFXForm_1_ext<31, 339, 8, (outs G8RC:$rT), (ins),
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let PPC970_Unit = 1 in { // FXU Operations.
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def LI8 : DForm_2_r0<14, (outs G8RC:$rD), (ins symbolLo64:$imm),
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"li $rD, $imm", IntGeneral,
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"li $rD, $imm", IntSimple,
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[(set G8RC:$rD, immSExt16:$imm)]>;
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def LIS8 : DForm_2_r0<15, (outs G8RC:$rD), (ins symbolHi64:$imm),
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"lis $rD, $imm", IntGeneral,
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"lis $rD, $imm", IntSimple,
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[(set G8RC:$rD, imm16ShiftedSExt:$imm)]>;
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// Logical ops.
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def NAND8: XForm_6<31, 476, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB),
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"nand $rA, $rS, $rB", IntGeneral,
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"nand $rA, $rS, $rB", IntSimple,
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[(set G8RC:$rA, (not (and G8RC:$rS, G8RC:$rB)))]>;
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def AND8 : XForm_6<31, 28, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB),
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"and $rA, $rS, $rB", IntGeneral,
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"and $rA, $rS, $rB", IntSimple,
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[(set G8RC:$rA, (and G8RC:$rS, G8RC:$rB))]>;
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def ANDC8: XForm_6<31, 60, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB),
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"andc $rA, $rS, $rB", IntGeneral,
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"andc $rA, $rS, $rB", IntSimple,
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[(set G8RC:$rA, (and G8RC:$rS, (not G8RC:$rB)))]>;
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def OR8 : XForm_6<31, 444, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB),
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"or $rA, $rS, $rB", IntGeneral,
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"or $rA, $rS, $rB", IntSimple,
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[(set G8RC:$rA, (or G8RC:$rS, G8RC:$rB))]>;
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def NOR8 : XForm_6<31, 124, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB),
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"nor $rA, $rS, $rB", IntGeneral,
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"nor $rA, $rS, $rB", IntSimple,
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[(set G8RC:$rA, (not (or G8RC:$rS, G8RC:$rB)))]>;
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def ORC8 : XForm_6<31, 412, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB),
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"orc $rA, $rS, $rB", IntGeneral,
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"orc $rA, $rS, $rB", IntSimple,
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[(set G8RC:$rA, (or G8RC:$rS, (not G8RC:$rB)))]>;
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def EQV8 : XForm_6<31, 284, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB),
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"eqv $rA, $rS, $rB", IntGeneral,
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"eqv $rA, $rS, $rB", IntSimple,
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[(set G8RC:$rA, (not (xor G8RC:$rS, G8RC:$rB)))]>;
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def XOR8 : XForm_6<31, 316, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB),
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"xor $rA, $rS, $rB", IntGeneral,
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"xor $rA, $rS, $rB", IntSimple,
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[(set G8RC:$rA, (xor G8RC:$rS, G8RC:$rB))]>;
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// Logical ops with immediate.
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@ -330,20 +330,20 @@ def ANDISo8 : DForm_4<29, (outs G8RC:$dst), (ins G8RC:$src1, u16imm:$src2),
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[(set G8RC:$dst, (and G8RC:$src1,imm16ShiftedZExt:$src2))]>,
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isDOT;
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def ORI8 : DForm_4<24, (outs G8RC:$dst), (ins G8RC:$src1, u16imm:$src2),
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"ori $dst, $src1, $src2", IntGeneral,
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"ori $dst, $src1, $src2", IntSimple,
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[(set G8RC:$dst, (or G8RC:$src1, immZExt16:$src2))]>;
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def ORIS8 : DForm_4<25, (outs G8RC:$dst), (ins G8RC:$src1, u16imm:$src2),
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"oris $dst, $src1, $src2", IntGeneral,
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"oris $dst, $src1, $src2", IntSimple,
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[(set G8RC:$dst, (or G8RC:$src1, imm16ShiftedZExt:$src2))]>;
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def XORI8 : DForm_4<26, (outs G8RC:$dst), (ins G8RC:$src1, u16imm:$src2),
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"xori $dst, $src1, $src2", IntGeneral,
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"xori $dst, $src1, $src2", IntSimple,
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[(set G8RC:$dst, (xor G8RC:$src1, immZExt16:$src2))]>;
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def XORIS8 : DForm_4<27, (outs G8RC:$dst), (ins G8RC:$src1, u16imm:$src2),
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"xoris $dst, $src1, $src2", IntGeneral,
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"xoris $dst, $src1, $src2", IntSimple,
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[(set G8RC:$dst, (xor G8RC:$src1, imm16ShiftedZExt:$src2))]>;
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def ADD8 : XOForm_1<31, 266, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB),
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"add $rT, $rA, $rB", IntGeneral,
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"add $rT, $rA, $rB", IntSimple,
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[(set G8RC:$rT, (add G8RC:$rA, G8RC:$rB))]>;
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let Defs = [CARRY] in {
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@ -356,13 +356,13 @@ def ADDIC8 : DForm_2<12, (outs G8RC:$rD), (ins G8RC:$rA, s16imm64:$imm),
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[(set G8RC:$rD, (addc G8RC:$rA, immSExt16:$imm))]>;
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}
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def ADDI8 : DForm_2<14, (outs G8RC:$rD), (ins G8RC:$rA, s16imm64:$imm),
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"addi $rD, $rA, $imm", IntGeneral,
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"addi $rD, $rA, $imm", IntSimple,
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[(set G8RC:$rD, (add G8RC:$rA, immSExt16:$imm))]>;
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def ADDI8L : DForm_2<14, (outs G8RC:$rD), (ins G8RC:$rA, symbolLo64:$imm),
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"addi $rD, $rA, $imm", IntGeneral,
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"addi $rD, $rA, $imm", IntSimple,
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[(set G8RC:$rD, (add G8RC:$rA, immSExt16:$imm))]>;
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def ADDIS8 : DForm_2<15, (outs G8RC:$rD), (ins G8RC:$rA, symbolHi64:$imm),
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"addis $rD, $rA, $imm", IntGeneral,
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"addis $rD, $rA, $imm", IntSimple,
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[(set G8RC:$rD, (add G8RC:$rA, imm16ShiftedSExt:$imm))]>;
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let Defs = [CARRY] in {
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@ -378,7 +378,7 @@ def SUBF8 : XOForm_1<31, 40, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB),
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"subf $rT, $rA, $rB", IntGeneral,
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[(set G8RC:$rT, (sub G8RC:$rB, G8RC:$rA))]>;
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def NEG8 : XOForm_3<31, 104, 0, (outs G8RC:$rT), (ins G8RC:$rA),
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"neg $rT, $rA", IntGeneral,
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"neg $rT, $rA", IntSimple,
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[(set G8RC:$rT, (ineg G8RC:$rA))]>;
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let Uses = [CARRY], Defs = [CARRY] in {
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def ADDE8 : XOForm_1<31, 138, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB),
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@ -431,21 +431,21 @@ def SRAD : XForm_6<31, 794, (outs G8RC:$rA), (ins G8RC:$rS, GPRC:$rB),
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}
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def EXTSB8 : XForm_11<31, 954, (outs G8RC:$rA), (ins G8RC:$rS),
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"extsb $rA, $rS", IntGeneral,
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"extsb $rA, $rS", IntSimple,
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[(set G8RC:$rA, (sext_inreg G8RC:$rS, i8))]>;
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def EXTSH8 : XForm_11<31, 922, (outs G8RC:$rA), (ins G8RC:$rS),
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"extsh $rA, $rS", IntGeneral,
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"extsh $rA, $rS", IntSimple,
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[(set G8RC:$rA, (sext_inreg G8RC:$rS, i16))]>;
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def EXTSW : XForm_11<31, 986, (outs G8RC:$rA), (ins G8RC:$rS),
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"extsw $rA, $rS", IntGeneral,
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"extsw $rA, $rS", IntSimple,
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[(set G8RC:$rA, (sext_inreg G8RC:$rS, i32))]>, isPPC64;
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/// EXTSW_32 - Just like EXTSW, but works on '32-bit' registers.
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def EXTSW_32 : XForm_11<31, 986, (outs GPRC:$rA), (ins GPRC:$rS),
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"extsw $rA, $rS", IntGeneral,
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"extsw $rA, $rS", IntSimple,
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[(set GPRC:$rA, (PPCextsw_32 GPRC:$rS))]>, isPPC64;
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def EXTSW_32_64 : XForm_11<31, 986, (outs G8RC:$rA), (ins GPRC:$rS),
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"extsw $rA, $rS", IntGeneral,
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"extsw $rA, $rS", IntSimple,
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[(set G8RC:$rA, (sext GPRC:$rS))]>, isPPC64;
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let Defs = [CARRY] in {
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@ -859,10 +859,10 @@ def SYNC : XForm_24_sync<31, 598, (outs), (ins),
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let PPC970_Unit = 1 in { // FXU Operations.
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def ADDI : DForm_2<14, (outs GPRC:$rD), (ins GPRC:$rA, s16imm:$imm),
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"addi $rD, $rA, $imm", IntGeneral,
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"addi $rD, $rA, $imm", IntSimple,
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[(set GPRC:$rD, (add GPRC:$rA, immSExt16:$imm))]>;
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def ADDIL : DForm_2<14, (outs GPRC:$rD), (ins GPRC:$rA, symbolLo:$imm),
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"addi $rD, $rA, $imm", IntGeneral,
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"addi $rD, $rA, $imm", IntSimple,
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[(set GPRC:$rD, (add GPRC:$rA, immSExt16:$imm))]>;
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let Defs = [CARRY] in {
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def ADDIC : DForm_2<12, (outs GPRC:$rD), (ins GPRC:$rA, s16imm:$imm),
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@ -874,7 +874,7 @@ def ADDICo : DForm_2<13, (outs GPRC:$rD), (ins GPRC:$rA, s16imm:$imm),
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[]>;
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}
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def ADDIS : DForm_2<15, (outs GPRC:$rD), (ins GPRC:$rA, symbolHi:$imm),
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"addis $rD, $rA, $imm", IntGeneral,
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"addis $rD, $rA, $imm", IntSimple,
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[(set GPRC:$rD, (add GPRC:$rA, imm16ShiftedSExt:$imm))]>;
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def LA : DForm_2<14, (outs GPRC:$rD), (ins GPRC:$rA, symbolLo:$sym),
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"la $rD, $sym($rA)", IntGeneral,
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@ -891,10 +891,10 @@ def SUBFIC : DForm_2< 8, (outs GPRC:$rD), (ins GPRC:$rA, s16imm:$imm),
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let isReMaterializable = 1 in {
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def LI : DForm_2_r0<14, (outs GPRC:$rD), (ins symbolLo:$imm),
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"li $rD, $imm", IntGeneral,
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"li $rD, $imm", IntSimple,
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[(set GPRC:$rD, immSExt16:$imm)]>;
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def LIS : DForm_2_r0<15, (outs GPRC:$rD), (ins symbolHi:$imm),
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"lis $rD, $imm", IntGeneral,
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"lis $rD, $imm", IntSimple,
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[(set GPRC:$rD, imm16ShiftedSExt:$imm)]>;
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}
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}
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@ -909,18 +909,18 @@ def ANDISo : DForm_4<29, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2),
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[(set GPRC:$dst, (and GPRC:$src1,imm16ShiftedZExt:$src2))]>,
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isDOT;
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def ORI : DForm_4<24, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2),
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"ori $dst, $src1, $src2", IntGeneral,
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"ori $dst, $src1, $src2", IntSimple,
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[(set GPRC:$dst, (or GPRC:$src1, immZExt16:$src2))]>;
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def ORIS : DForm_4<25, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2),
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"oris $dst, $src1, $src2", IntGeneral,
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"oris $dst, $src1, $src2", IntSimple,
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[(set GPRC:$dst, (or GPRC:$src1, imm16ShiftedZExt:$src2))]>;
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def XORI : DForm_4<26, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2),
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"xori $dst, $src1, $src2", IntGeneral,
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"xori $dst, $src1, $src2", IntSimple,
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[(set GPRC:$dst, (xor GPRC:$src1, immZExt16:$src2))]>;
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def XORIS : DForm_4<27, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2),
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"xoris $dst, $src1, $src2", IntGeneral,
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"xoris $dst, $src1, $src2", IntSimple,
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[(set GPRC:$dst, (xor GPRC:$src1,imm16ShiftedZExt:$src2))]>;
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def NOP : DForm_4_zero<24, (outs), (ins), "nop", IntGeneral,
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def NOP : DForm_4_zero<24, (outs), (ins), "nop", IntSimple,
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[]>;
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def CMPWI : DForm_5_ext<11, (outs CRRC:$crD), (ins GPRC:$rA, s16imm:$imm),
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"cmpwi $crD, $rA, $imm", IntCompare>;
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@ -931,28 +931,28 @@ def CMPLWI : DForm_6_ext<10, (outs CRRC:$dst), (ins GPRC:$src1, u16imm:$src2),
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let PPC970_Unit = 1 in { // FXU Operations.
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def NAND : XForm_6<31, 476, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
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"nand $rA, $rS, $rB", IntGeneral,
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"nand $rA, $rS, $rB", IntSimple,
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[(set GPRC:$rA, (not (and GPRC:$rS, GPRC:$rB)))]>;
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def AND : XForm_6<31, 28, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
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"and $rA, $rS, $rB", IntGeneral,
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"and $rA, $rS, $rB", IntSimple,
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[(set GPRC:$rA, (and GPRC:$rS, GPRC:$rB))]>;
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def ANDC : XForm_6<31, 60, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
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"andc $rA, $rS, $rB", IntGeneral,
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"andc $rA, $rS, $rB", IntSimple,
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[(set GPRC:$rA, (and GPRC:$rS, (not GPRC:$rB)))]>;
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def OR : XForm_6<31, 444, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
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"or $rA, $rS, $rB", IntGeneral,
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"or $rA, $rS, $rB", IntSimple,
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[(set GPRC:$rA, (or GPRC:$rS, GPRC:$rB))]>;
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def NOR : XForm_6<31, 124, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
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"nor $rA, $rS, $rB", IntGeneral,
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"nor $rA, $rS, $rB", IntSimple,
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[(set GPRC:$rA, (not (or GPRC:$rS, GPRC:$rB)))]>;
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def ORC : XForm_6<31, 412, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
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"orc $rA, $rS, $rB", IntGeneral,
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"orc $rA, $rS, $rB", IntSimple,
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[(set GPRC:$rA, (or GPRC:$rS, (not GPRC:$rB)))]>;
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def EQV : XForm_6<31, 284, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
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"eqv $rA, $rS, $rB", IntGeneral,
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"eqv $rA, $rS, $rB", IntSimple,
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[(set GPRC:$rA, (not (xor GPRC:$rS, GPRC:$rB)))]>;
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def XOR : XForm_6<31, 316, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
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"xor $rA, $rS, $rB", IntGeneral,
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"xor $rA, $rS, $rB", IntSimple,
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[(set GPRC:$rA, (xor GPRC:$rS, GPRC:$rB))]>;
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def SLW : XForm_6<31, 24, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
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"slw $rA, $rS, $rB", IntGeneral,
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@ -977,10 +977,10 @@ def CNTLZW : XForm_11<31, 26, (outs GPRC:$rA), (ins GPRC:$rS),
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"cntlzw $rA, $rS", IntGeneral,
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[(set GPRC:$rA, (ctlz GPRC:$rS))]>;
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def EXTSB : XForm_11<31, 954, (outs GPRC:$rA), (ins GPRC:$rS),
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"extsb $rA, $rS", IntGeneral,
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"extsb $rA, $rS", IntSimple,
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[(set GPRC:$rA, (sext_inreg GPRC:$rS, i8))]>;
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def EXTSH : XForm_11<31, 922, (outs GPRC:$rA), (ins GPRC:$rS),
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"extsh $rA, $rS", IntGeneral,
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"extsh $rA, $rS", IntSimple,
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[(set GPRC:$rA, (sext_inreg GPRC:$rS, i16))]>;
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def CMPW : XForm_16_ext<31, 0, (outs CRRC:$crD), (ins GPRC:$rA, GPRC:$rB),
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@ -1169,7 +1169,7 @@ let PPC970_Unit = 1 in { // FXU Operations.
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// XO-Form instructions. Arithmetic instructions that can set overflow bit
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//
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def ADD4 : XOForm_1<31, 266, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
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"add $rT, $rA, $rB", IntGeneral,
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"add $rT, $rA, $rB", IntSimple,
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[(set GPRC:$rT, (add GPRC:$rA, GPRC:$rB))]>;
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let Defs = [CARRY] in {
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def ADDC : XOForm_1<31, 10, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
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@ -1204,7 +1204,7 @@ def SUBFC : XOForm_1<31, 8, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
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PPC970_DGroup_Cracked;
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}
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def NEG : XOForm_3<31, 104, 0, (outs GPRC:$rT), (ins GPRC:$rA),
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"neg $rT, $rA", IntGeneral,
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"neg $rT, $rA", IntSimple,
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[(set GPRC:$rT, (ineg GPRC:$rA))]>;
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let Uses = [CARRY], Defs = [CARRY] in {
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def ADDE : XOForm_1<31, 138, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
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@ -25,6 +25,7 @@ def VFPU : FuncUnit; // vector floating point unit
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//===----------------------------------------------------------------------===//
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// Instruction Itinerary classes used for PowerPC
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//
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def IntSimple : InstrItinClass;
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def IntGeneral : InstrItinClass;
|
||||
def IntCompare : InstrItinClass;
|
||||
def IntDivD : InstrItinClass;
|
||||
@ -117,17 +118,17 @@ include "PPCScheduleA2.td"
|
||||
//
|
||||
// opcode itinerary class
|
||||
// ====== ===============
|
||||
// add IntGeneral
|
||||
// add IntSimple
|
||||
// addc IntGeneral
|
||||
// adde IntGeneral
|
||||
// addi IntGeneral
|
||||
// addi IntSimple
|
||||
// addic IntGeneral
|
||||
// addic. IntGeneral
|
||||
// addis IntGeneral
|
||||
// addis IntSimple
|
||||
// addme IntGeneral
|
||||
// addze IntGeneral
|
||||
// and IntGeneral
|
||||
// andc IntGeneral
|
||||
// and IntSimple
|
||||
// andc IntSimple
|
||||
// andi. IntGeneral
|
||||
// andis. IntGeneral
|
||||
// b BrB
|
||||
@ -165,10 +166,10 @@ include "PPCScheduleA2.td"
|
||||
// eciwx LdStLoad
|
||||
// ecowx LdStLoad
|
||||
// eieio LdStLoad
|
||||
// eqv IntGeneral
|
||||
// extsb IntGeneral
|
||||
// extsh IntGeneral
|
||||
// extsw IntRotateD
|
||||
// eqv IntSimple
|
||||
// extsb IntSimple
|
||||
// extsh IntSimple
|
||||
// extsw IntSimple
|
||||
// fabs FPGeneral
|
||||
// fadd FPGeneral
|
||||
// fadds FPGeneral
|
||||
@ -280,13 +281,13 @@ include "PPCScheduleA2.td"
|
||||
// mulld IntMulHD
|
||||
// mulli IntMulLI
|
||||
// mullw IntMulHW
|
||||
// nand IntGeneral
|
||||
// neg IntGeneral
|
||||
// nor IntGeneral
|
||||
// or IntGeneral
|
||||
// orc IntGeneral
|
||||
// ori IntGeneral
|
||||
// oris IntGeneral
|
||||
// nand IntSimple
|
||||
// neg IntSimple
|
||||
// nor IntSimple
|
||||
// or IntSimple
|
||||
// orc IntSimple
|
||||
// ori IntSimple
|
||||
// oris IntSimple
|
||||
// rfi SprRFI
|
||||
// rfid IntRFID
|
||||
// rldcl IntRotateD
|
||||
@ -502,7 +503,7 @@ include "PPCScheduleA2.td"
|
||||
// vupklsb VecPerm
|
||||
// vupklsh VecPerm
|
||||
// vxor VecGeneral
|
||||
// xor IntGeneral
|
||||
// xori IntGeneral
|
||||
// xoris IntGeneral
|
||||
// xor IntSimple
|
||||
// xori IntSimple
|
||||
// xoris IntSimple
|
||||
//
|
||||
|
||||
@ -108,6 +108,15 @@ def PPC440Itineraries : ProcessorItineraries<
|
||||
IRACC, IEXE1, IEXE2, IWB, LRACC, JEXE1, JEXE2, JWB, AGEN, CRD, LWB,
|
||||
FEXE1, FEXE2, FEXE3, FEXE4, FEXE5, FEXE6, FWB, LWARX_Hold],
|
||||
[GPR_Bypass, FPR_Bypass], [
|
||||
InstrItinData<IntSimple , [InstrStage<1, [IFTH1, IFTH2]>,
|
||||
InstrStage<1, [PDCD1, PDCD2]>,
|
||||
InstrStage<1, [DISS1, DISS2]>,
|
||||
InstrStage<1, [IRACC, LRACC]>,
|
||||
InstrStage<1, [IEXE1, JEXE1]>,
|
||||
InstrStage<1, [IEXE2, JEXE2]>,
|
||||
InstrStage<1, [IWB, JWB]>],
|
||||
[6, 4, 4],
|
||||
[GPR_Bypass, GPR_Bypass, GPR_Bypass]>,
|
||||
InstrItinData<IntGeneral , [InstrStage<1, [IFTH1, IFTH2]>,
|
||||
InstrStage<1, [PDCD1, PDCD2]>,
|
||||
InstrStage<1, [DISS1, DISS2]>,
|
||||
|
||||
@ -60,6 +60,17 @@ def PPCA2Itineraries : ProcessorItineraries<
|
||||
IU5, IU6, RF0, XRF1, XEX1, XEX2, XEX3, XEX4, XEX5, XEX6,
|
||||
FRF1, FEX1, FEX2, FEX3, FEX4, FEX5, FEX6],
|
||||
[CR_Bypass, GPR_Bypass, FPR_Bypass], [
|
||||
InstrItinData<IntSimple , [InstrStage<4,
|
||||
[IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
|
||||
InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
|
||||
IU4_4, IU4_5, IU4_6, IU4_7]>,
|
||||
InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
|
||||
InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
|
||||
InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
|
||||
InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
|
||||
InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
|
||||
[10, 7, 7],
|
||||
[GPR_Bypass, GPR_Bypass, GPR_Bypass]>,
|
||||
InstrItinData<IntGeneral , [InstrStage<4,
|
||||
[IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
|
||||
InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
|
||||
|
||||
@ -14,6 +14,7 @@
|
||||
|
||||
def G3Itineraries : ProcessorItineraries<
|
||||
[IU1, IU2, FPU1, BPU, SRU, SLU], [], [
|
||||
InstrItinData<IntSimple , [InstrStage<1, [IU1, IU2]>]>,
|
||||
InstrItinData<IntGeneral , [InstrStage<1, [IU1, IU2]>]>,
|
||||
InstrItinData<IntCompare , [InstrStage<1, [IU1, IU2]>]>,
|
||||
InstrItinData<IntDivW , [InstrStage<19, [IU1]>]>,
|
||||
|
||||
@ -13,6 +13,7 @@
|
||||
|
||||
def G4Itineraries : ProcessorItineraries<
|
||||
[IU1, IU2, SLU, SRU, BPU, FPU1, VIU1, VIU2, VPU, VFPU], [], [
|
||||
InstrItinData<IntSimple , [InstrStage<1, [IU1, IU2]>]>,
|
||||
InstrItinData<IntGeneral , [InstrStage<1, [IU1, IU2]>]>,
|
||||
InstrItinData<IntCompare , [InstrStage<1, [IU1, IU2]>]>,
|
||||
InstrItinData<IntDivW , [InstrStage<19, [IU1]>]>,
|
||||
|
||||
@ -16,6 +16,7 @@ def IU4 : FuncUnit; // integer unit 4 (7450 simple)
|
||||
|
||||
def G4PlusItineraries : ProcessorItineraries<
|
||||
[IU1, IU2, IU3, IU4, BPU, SLU, FPU1, VFPU, VIU1, VIU2, VPU], [], [
|
||||
InstrItinData<IntSimple , [InstrStage<1, [IU1, IU2, IU3, IU4]>]>,
|
||||
InstrItinData<IntGeneral , [InstrStage<1, [IU1, IU2, IU3, IU4]>]>,
|
||||
InstrItinData<IntCompare , [InstrStage<1, [IU1, IU2, IU3, IU4]>]>,
|
||||
InstrItinData<IntDivW , [InstrStage<23, [IU2]>]>,
|
||||
|
||||
@ -13,6 +13,7 @@
|
||||
|
||||
def G5Itineraries : ProcessorItineraries<
|
||||
[IU1, IU2, SLU, BPU, FPU1, FPU2, VFPU, VIU1, VIU2, VPU], [], [
|
||||
InstrItinData<IntSimple , [InstrStage<2, [IU1, IU2]>]>,
|
||||
InstrItinData<IntGeneral , [InstrStage<2, [IU1, IU2]>]>,
|
||||
InstrItinData<IntCompare , [InstrStage<3, [IU1, IU2]>]>,
|
||||
InstrItinData<IntDivD , [InstrStage<68, [IU1]>]>,
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user