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Added ARM::CPSR to represent ARM CPSR status register.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37897 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng 2007-07-05 07:17:13 +00:00
parent ee568cf794
commit 16b6598325
1 changed files with 6 additions and 0 deletions
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6
lib/Target/ARM/ARMRegisterInfo.td
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@ -78,6 +78,9 @@ def D13 : ARMReg<13, "d13", [S26, S27]>;
def D14 : ARMReg<14, "d14", [S28, S29]>; def D14 : ARMReg<14, "d14", [S28, S29]>;
def D15 : ARMReg<15, "d15", [S30, S31]>; def D15 : ARMReg<15, "d15", [S30, S31]>;
// Current Program Status Register.
def CPSR : ARMReg<0, "cpsr">;
// Register classes. // Register classes.
// //
// pc == Program Counter // pc == Program Counter
@ -188,3 +191,6 @@ def SPR : RegisterClass<"ARM", [f32], 32, [S0, S1, S2, S3, S4, S5, S6, S7, S8,
// is double-word alignment though. // is double-word alignment though.
def DPR : RegisterClass<"ARM", [f64], 64, [D0, D1, D2, D3, D4, D5, D6, D7, D8, def DPR : RegisterClass<"ARM", [f64], 64, [D0, D1, D2, D3, D4, D5, D6, D7, D8,
D9, D10, D11, D12, D13, D14, D15]>; D9, D10, D11, D12, D13, D14, D15]>;
// Condition code registers.
def CCR : RegisterClass<"ARM", [i32], 32, [CPSR]>;