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[mips][microMIPS] Implement ADDIUPC instruction

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Differential Revision: http://reviews.llvm.org/D6582


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@226656 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jozef Kolek
2015-01-21 12:10:11 +00:00
parent 9d4f87e9be
commit 16dbcd741f
10 changed files with 86 additions and 0 deletions
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9
lib/Target/Mips/Disassembler/MipsDisassembler.cpp
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@@ -370,6 +370,9 @@ static DecodeStatus DecodeANDI16Imm(MCInst &Inst, unsigned Insn,
static DecodeStatus DecodeUImm5lsl2(MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder);
static DecodeStatus DecodeSimm23Lsl2(MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder);
/// INSVE_[BHWD] have an implicit operand that the generated decoder doesn't
/// handle.
template <typename InsnType>
@@ -1756,3 +1759,9 @@ static DecodeStatus DecodeRegListOperand16(MCInst &Inst, unsigned Insn,
return MCDisassembler::Success;
}
static DecodeStatus DecodeSimm23Lsl2(MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder) {
Inst.addOperand(MCOperand::CreateImm(SignExtend32<23>(Insn) << 2));
return MCDisassembler::Success;
}