6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-10-30 16:17:05 +00:00
Code Issues Projects Releases Wiki Activity

Pseudo-ize the t2LDMIA_RET instruction.

Browse Source 
It's just a t2LDMIA_UPD instruction with extra codegen properties, so it
doesn't need the encoding information. As a side-benefit, we now correctly
recognize for instruction printing as a 'pop' instruction.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134173 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jim Grosbach
2011-06-30 18:25:42 +00:00
parent 4629d50501
commit 16f9924000
3 changed files with 13 additions and 20 deletions
Download Patch File Download Diff File Expand all files Collapse all files

8
lib/Target/ARM/ARMAsmPrinter.cpp
View File

@@ -1096,6 +1096,14 @@ void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) {
OutStreamer.EmitInstruction(TmpInst); OutStreamer.EmitInstruction(TmpInst);
return; return;
} }
case ARM::t2LDMIA_RET: {
// As above for LDMIA_RET. Map to the tPOP instruction.
MCInst TmpInst;
LowerARMMachineInstrToMCInst(MI, TmpInst, *this);
TmpInst.setOpcode(ARM::t2LDMIA_UPD);
OutStreamer.EmitInstruction(TmpInst);
return;
}
case ARM::tPOP_RET: { case ARM::tPOP_RET: {
// As above for LDMIA_RET. Map to the tPOP instruction. // As above for LDMIA_RET. Map to the tPOP instruction.
MCInst TmpInst; MCInst TmpInst;

21
lib/Target/ARM/ARMInstrThumb2.td
View File

@@ -2962,28 +2962,13 @@ let Defs =
// //
// FIXME: remove when we have a way to marking a MI with these properties. // FIXME: remove when we have a way to marking a MI with these properties.
// FIXME: $dst1 should be a def. But the extra ops must be in the end of the
// operand list.
// FIXME: Should pc be an implicit operand like PICADD, etc? // FIXME: Should pc be an implicit operand like PICADD, etc?
let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1, let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
hasExtraDefRegAllocReq = 1, isCodeGenOnly = 1 in hasExtraDefRegAllocReq = 1, isCodeGenOnly = 1 in
def t2LDMIA_RET: T2XIt<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, def t2LDMIA_RET: t2PseudoInst<(outs GPR:$wb), (ins GPR:$Rn, pred:$p,
reglist:$regs, variable_ops), reglist:$regs, variable_ops),
IIC_iLoad_mBr, Size4Bytes, IIC_iLoad_mBr, []>,
"ldmia${p}.w\t$Rn!, $regs", RegConstraint<"$Rn = $wb">;
"$Rn = $wb", []> {
bits<4> Rn;
bits<16> regs;
let Inst{31-27} = 0b11101;
let Inst{26-25} = 0b00;
let Inst{24-23} = 0b01; // Increment After
let Inst{22} = 0;
let Inst{21} = 1; // Writeback
let Inst{20} = 1;
let Inst{19-16} = Rn;
let Inst{15-0} = regs;
}
let isBranch = 1, isTerminator = 1, isBarrier = 1 in { let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
let isPredicable = 1 in let isPredicable = 1 in

2
test/CodeGen/Thumb2/2009-10-15-ITBlockBranch.ll
View File

@@ -13,7 +13,7 @@ define weak arm_aapcs_vfpcc i32 @_ZNKSs7compareERKSs(%"struct.std::basic_string<
; CHECK: _ZNKSs7compareERKSs: ; CHECK: _ZNKSs7compareERKSs:
; CHECK: it eq ; CHECK: it eq
; CHECK-NEXT: subeq{{(.w)?}} r0, r{{[0-9]+}}, r{{[0-9]+}} ; CHECK-NEXT: subeq{{(.w)?}} r0, r{{[0-9]+}}, r{{[0-9]+}}
; CHECK-NEXT: ldmia.w sp!, ; CHECK-NEXT: pop.w
entry: entry:
%0 = tail call arm_aapcs_vfpcc i32 @_ZNKSs4sizeEv(%"struct.std::basic_string<char,std::char_traits<char>,std::allocator<char> >"* %this) ; <i32> [#uses=3] %0 = tail call arm_aapcs_vfpcc i32 @_ZNKSs4sizeEv(%"struct.std::basic_string<char,std::char_traits<char>,std::allocator<char> >"* %this) ; <i32> [#uses=3]
%1 = tail call arm_aapcs_vfpcc i32 @_ZNKSs4sizeEv(%"struct.std::basic_string<char,std::char_traits<char>,std::allocator<char> >"* %__str) ; <i32> [#uses=3] %1 = tail call arm_aapcs_vfpcc i32 @_ZNKSs4sizeEv(%"struct.std::basic_string<char,std::char_traits<char>,std::allocator<char> >"* %__str) ; <i32> [#uses=3]