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R600/SI: Refactor the VOP3_32 tablegen class

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This will allow us to use a single MachineInstr to represent
instructions which behave the same but have different encodings
on some subtargets.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209028 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Tom Stellard
2014-05-16 20:56:47 +00:00
parent 9d99d7a185
commit 17200e3bb3
6 changed files with 112 additions and 34 deletions
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11
lib/Target/R600/AMDGPUInstrInfo.cpp
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@@ -355,3 +355,14 @@ int AMDGPUInstrInfo::getMaskedMIMGOp(uint16_t Opcode, unsigned Channels) const {
case 3: return AMDGPU::getMaskedMIMGOp(Opcode, AMDGPU::Channels_3);
}
}
// Wrapper for Tablegen'd function. enum Subtarget is not defined in any
// header files, so we need to wrap it in a function that takes unsigned
// instead.
namespace llvm {
namespace AMDGPU {
int getMCOpcode(uint16_t Opcode, unsigned Gen) {
return getMCOpcode(Opcode);
}
}
}