inline asm, at least for floats

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28895 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/Alpha/AlphaAsmPrinter.cpp

@@ -59,6 +59,9 @@ namespace {
     bool runOnMachineFunction(MachineFunction &F);
     bool doInitialization(Module &M);
     bool doFinalization(Module &M);
+
+    bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
+                         unsigned AsmVariant, const char *ExtraCode);
   };
 } // end of anonymous namespace
 
@@ -265,3 +268,12 @@ bool AlphaAsmPrinter::doFinalization(Module &M) {
   AsmPrinter::doFinalization(M);
   return false;
 }
+
+/// PrintAsmOperand - Print out an operand for an inline asm expression.
+///
+bool AlphaAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
+                                    unsigned AsmVariant, 
+                                    const char *ExtraCode) {
+  printOperand(MI, OpNo);
+  return false;
+}

lib/Target/Alpha/AlphaISelLowering.cpp

@@ -580,3 +580,42 @@ SDOperand AlphaTargetLowering::CustomPromoteOperation(SDOperand Op,
   // The code in LowerOperation already handles i32 vaarg
   return LowerOperation(Op, DAG);
 }
+
+
+//Inline Asm
+
+/// getConstraintType - Given a constraint letter, return the type of
+/// constraint it is for this target.
+AlphaTargetLowering::ConstraintType 
+AlphaTargetLowering::getConstraintType(char ConstraintLetter) const {
+  switch (ConstraintLetter) {
+  default: break;
+  case 'f':
+    return C_RegisterClass;
+  }  
+  return TargetLowering::getConstraintType(ConstraintLetter);
+}
+
+std::vector<unsigned> AlphaTargetLowering::
+getRegClassForInlineAsmConstraint(const std::string &Constraint,
+                                  MVT::ValueType VT) const {
+  if (Constraint.size() == 1) {
+    switch (Constraint[0]) {
+    default: break;  // Unknown constriant letter
+    case 'f': 
+      return make_vector<unsigned>(Alpha::F0 , Alpha::F1 , Alpha::F2 ,
+				   Alpha::F3 , Alpha::F4 , Alpha::F5 , 
+				   Alpha::F6 , Alpha::F7 , Alpha::F8 , 
+				   Alpha::F9 , Alpha::F10, Alpha::F11, 
+                                   Alpha::F12, Alpha::F13, Alpha::F14, 
+				   Alpha::F15, Alpha::F16, Alpha::F17, 
+				   Alpha::F18, Alpha::F19, Alpha::F20, 
+				   Alpha::F21, Alpha::F22, Alpha::F23, 
+                                   Alpha::F24, Alpha::F25, Alpha::F26, 
+				   Alpha::F27, Alpha::F28, Alpha::F29, 
+				   Alpha::F30, Alpha::F31, 0);
+    }
+  }
+  
+  return std::vector<unsigned>();
+}

lib/Target/Alpha/AlphaISelLowering.h

@@ -15,6 +15,7 @@
 #ifndef LLVM_TARGET_ALPHA_ALPHAISELLOWERING_H
 #define LLVM_TARGET_ALPHA_ALPHAISELLOWERING_H
 
+#include "llvm/ADT/VectorExtras.h"
 #include "llvm/Target/TargetLowering.h"
 #include "llvm/CodeGen/SelectionDAG.h"
 #include "Alpha.h"
@@ -77,6 +78,12 @@ namespace llvm {
                 bool isTailCall, SDOperand Callee, ArgListTy &Args,
                 SelectionDAG &DAG);
 
+    ConstraintType getConstraintType(char ConstraintLetter) const;
+
+    std::vector<unsigned> 
+      getRegClassForInlineAsmConstraint(const std::string &Constraint,
+                                        MVT::ValueType VT) const;
+
     void restoreGP(MachineBasicBlock* BB);
     void restoreRA(MachineBasicBlock* BB);
     unsigned getVRegGP() { return GP; }