mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2025-01-26 23:32:58 +00:00
Add instruction selection code and tests for setcc instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4603 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Brian Gaeke
parent
ed8e6499dd
commit
1749d6359b
@ -8,6 +8,7 @@
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#include "X86InstrInfo.h"
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#include "llvm/Function.h"
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#include "llvm/iTerminators.h"
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#include "llvm/iOperators.h"
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#include "llvm/iOther.h"
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#include "llvm/iPHINode.h"
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#include "llvm/Type.h"
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@ -77,6 +78,7 @@ namespace {
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// Other operators
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void visitShiftInst(ShiftInst &I);
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void visitSetCondInst(SetCondInst &I);
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void visitPHINode(PHINode &I);
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void visitInstruction(Instruction &I) {
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@ -160,6 +162,157 @@ void ISel::copyConstantToRegister(Constant *C, unsigned R) {
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}
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}
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/// SetCC instructions - Here we just emit boilerplate code to set a byte-sized
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/// register, then move it to wherever the result should be.
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/// We handle FP setcc instructions by pushing them, doing a
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/// compare-and-pop-twice, and then copying the concodes to the main
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/// processor's concodes (I didn't make this up, it's in the Intel manual)
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///
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void
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ISel::visitSetCondInst (SetCondInst & I)
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{
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// The arguments are already supposed to be of the same type.
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Value *var1 = I.getOperand (0);
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Value *var2 = I.getOperand (1);
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unsigned reg1 = getReg (var1);
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unsigned reg2 = getReg (var2);
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unsigned resultReg = getReg (I);
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unsigned comparisonWidth = var1->getType ()->getPrimitiveSize ();
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unsigned unsignedComparison = var1->getType ()->isUnsigned ();
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unsigned resultWidth = I.getType ()->getPrimitiveSize ();
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bool fpComparison = var1->getType ()->isFloatingPoint ();
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if (fpComparison)
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{
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// Push the variables on the stack with fldl opcodes.
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// FIXME: assuming var1, var2 are in memory, if not, spill to
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// stack first
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switch (comparisonWidth)
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{
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case 4:
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BuildMI (BB, X86::FLDr4, 1, X86::NoReg).addReg (reg1);
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break;
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case 8:
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BuildMI (BB, X86::FLDr8, 1, X86::NoReg).addReg (reg1);
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break;
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default:
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visitInstruction (I);
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break;
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}
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switch (comparisonWidth)
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{
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case 4:
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BuildMI (BB, X86::FLDr4, 1, X86::NoReg).addReg (reg2);
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break;
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case 8:
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BuildMI (BB, X86::FLDr8, 1, X86::NoReg).addReg (reg2);
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break;
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default:
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visitInstruction (I);
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break;
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}
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// (Non-trapping) compare and pop twice.
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// FIXME: Result of comparison -> condition codes, not a register.
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BuildMI (BB, X86::FUCOMPP, 0);
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// Move fp status word (concodes) to ax.
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BuildMI (BB, X86::FNSTSWr8, 1, X86::AX);
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// Load real concodes from ax.
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// FIXME: Once again, flags are not modeled.
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BuildMI (BB, X86::SAHF, 0);
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}
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else
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{ // integer comparison
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// Emit: cmp <var1>, <var2> (do the comparison). We can
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// compare 8-bit with 8-bit, 16-bit with 16-bit, 32-bit with
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// 32-bit.
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// FIXME: Result of comparison -> condition codes, not a register.
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switch (comparisonWidth)
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{
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case 1:
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BuildMI (BB, X86::CMPrr8, 2,
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X86::NoReg).addReg (reg1).addReg (reg2);
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break;
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case 2:
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BuildMI (BB, X86::CMPrr16, 2,
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X86::NoReg).addReg (reg1).addReg (reg2);
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break;
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case 4:
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BuildMI (BB, X86::CMPrr32, 2,
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X86::NoReg).addReg (reg1).addReg (reg2);
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break;
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case 8:
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default:
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visitInstruction (I);
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break;
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}
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}
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// Emit setOp instruction (extract concode; clobbers ax),
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// using the following mapping:
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// LLVM -> X86 signed X86 unsigned
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// ----- ----- -----
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// seteq -> sete sete
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// setne -> setne setne
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// setlt -> setl setb
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// setgt -> setg seta
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// setle -> setle setbe
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// setge -> setge setae
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switch (I.getOpcode ())
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{
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case Instruction::SetEQ:
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BuildMI (BB, X86::SETE, 0, X86::AL);
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break;
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case Instruction::SetGE:
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if (unsignedComparison)
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BuildMI (BB, X86::SETAE, 0, X86::AL);
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else
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BuildMI (BB, X86::SETGE, 0, X86::AL);
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break;
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case Instruction::SetGT:
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if (unsignedComparison)
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BuildMI (BB, X86::SETA, 0, X86::AL);
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else
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BuildMI (BB, X86::SETG, 0, X86::AL);
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break;
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case Instruction::SetLE:
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if (unsignedComparison)
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BuildMI (BB, X86::SETBE, 0, X86::AL);
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else
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BuildMI (BB, X86::SETLE, 0, X86::AL);
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break;
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case Instruction::SetLT:
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if (unsignedComparison)
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BuildMI (BB, X86::SETB, 0, X86::AL);
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else
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BuildMI (BB, X86::SETL, 0, X86::AL);
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break;
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case Instruction::SetNE:
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BuildMI (BB, X86::SETNE, 0, X86::AL);
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break;
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default:
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visitInstruction (I);
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break;
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}
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// Put it in the result using a move.
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switch (resultWidth)
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{
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case 1:
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BuildMI (BB, X86::MOVrr8, 1, resultReg).addReg (X86::AL);
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break;
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// FIXME: What to do about implicit destination registers?
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// E.g., you don't specify it, but CBW is more like AX = CBW(AL).
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case 2:
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BuildMI (BB, X86::CBW, 0, X86::AX);
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BuildMI (BB, X86::MOVrr16, 1, resultReg).addReg (X86::AX);
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break;
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case 4:
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BuildMI (BB, X86::CWDE, 0, X86::EAX);
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BuildMI (BB, X86::MOVrr32, 1, resultReg).addReg (X86::EAX);
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break;
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case 8:
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default:
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visitInstruction (I);
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break;
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}
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}
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/// 'ret' instruction - Here we are interested in meeting the x86 ABI. As such,
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@ -8,6 +8,7 @@
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#include "X86InstrInfo.h"
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#include "llvm/Function.h"
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#include "llvm/iTerminators.h"
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#include "llvm/iOperators.h"
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#include "llvm/iOther.h"
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#include "llvm/iPHINode.h"
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#include "llvm/Type.h"
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@ -77,6 +78,7 @@ namespace {
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// Other operators
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void visitShiftInst(ShiftInst &I);
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void visitSetCondInst(SetCondInst &I);
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void visitPHINode(PHINode &I);
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void visitInstruction(Instruction &I) {
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@ -160,6 +162,157 @@ void ISel::copyConstantToRegister(Constant *C, unsigned R) {
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}
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}
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/// SetCC instructions - Here we just emit boilerplate code to set a byte-sized
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/// register, then move it to wherever the result should be.
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/// We handle FP setcc instructions by pushing them, doing a
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/// compare-and-pop-twice, and then copying the concodes to the main
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/// processor's concodes (I didn't make this up, it's in the Intel manual)
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///
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void
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ISel::visitSetCondInst (SetCondInst & I)
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{
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// The arguments are already supposed to be of the same type.
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Value *var1 = I.getOperand (0);
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Value *var2 = I.getOperand (1);
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unsigned reg1 = getReg (var1);
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unsigned reg2 = getReg (var2);
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unsigned resultReg = getReg (I);
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unsigned comparisonWidth = var1->getType ()->getPrimitiveSize ();
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unsigned unsignedComparison = var1->getType ()->isUnsigned ();
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unsigned resultWidth = I.getType ()->getPrimitiveSize ();
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bool fpComparison = var1->getType ()->isFloatingPoint ();
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if (fpComparison)
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{
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// Push the variables on the stack with fldl opcodes.
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// FIXME: assuming var1, var2 are in memory, if not, spill to
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// stack first
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switch (comparisonWidth)
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{
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case 4:
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BuildMI (BB, X86::FLDr4, 1, X86::NoReg).addReg (reg1);
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break;
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case 8:
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BuildMI (BB, X86::FLDr8, 1, X86::NoReg).addReg (reg1);
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break;
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default:
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visitInstruction (I);
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break;
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}
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switch (comparisonWidth)
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{
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case 4:
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BuildMI (BB, X86::FLDr4, 1, X86::NoReg).addReg (reg2);
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break;
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case 8:
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BuildMI (BB, X86::FLDr8, 1, X86::NoReg).addReg (reg2);
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break;
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default:
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visitInstruction (I);
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break;
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}
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// (Non-trapping) compare and pop twice.
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// FIXME: Result of comparison -> condition codes, not a register.
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BuildMI (BB, X86::FUCOMPP, 0);
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// Move fp status word (concodes) to ax.
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BuildMI (BB, X86::FNSTSWr8, 1, X86::AX);
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// Load real concodes from ax.
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// FIXME: Once again, flags are not modeled.
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BuildMI (BB, X86::SAHF, 0);
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}
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else
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{ // integer comparison
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// Emit: cmp <var1>, <var2> (do the comparison). We can
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// compare 8-bit with 8-bit, 16-bit with 16-bit, 32-bit with
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// 32-bit.
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// FIXME: Result of comparison -> condition codes, not a register.
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switch (comparisonWidth)
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{
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case 1:
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BuildMI (BB, X86::CMPrr8, 2,
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X86::NoReg).addReg (reg1).addReg (reg2);
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break;
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case 2:
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BuildMI (BB, X86::CMPrr16, 2,
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X86::NoReg).addReg (reg1).addReg (reg2);
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break;
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case 4:
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BuildMI (BB, X86::CMPrr32, 2,
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X86::NoReg).addReg (reg1).addReg (reg2);
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break;
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case 8:
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default:
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visitInstruction (I);
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break;
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}
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}
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// Emit setOp instruction (extract concode; clobbers ax),
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// using the following mapping:
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// LLVM -> X86 signed X86 unsigned
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// ----- ----- -----
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// seteq -> sete sete
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// setne -> setne setne
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// setlt -> setl setb
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// setgt -> setg seta
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// setle -> setle setbe
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// setge -> setge setae
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switch (I.getOpcode ())
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{
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case Instruction::SetEQ:
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BuildMI (BB, X86::SETE, 0, X86::AL);
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break;
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case Instruction::SetGE:
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if (unsignedComparison)
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BuildMI (BB, X86::SETAE, 0, X86::AL);
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else
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BuildMI (BB, X86::SETGE, 0, X86::AL);
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break;
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case Instruction::SetGT:
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if (unsignedComparison)
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BuildMI (BB, X86::SETA, 0, X86::AL);
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else
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BuildMI (BB, X86::SETG, 0, X86::AL);
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break;
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case Instruction::SetLE:
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if (unsignedComparison)
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BuildMI (BB, X86::SETBE, 0, X86::AL);
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else
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BuildMI (BB, X86::SETLE, 0, X86::AL);
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break;
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case Instruction::SetLT:
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if (unsignedComparison)
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BuildMI (BB, X86::SETB, 0, X86::AL);
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else
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BuildMI (BB, X86::SETL, 0, X86::AL);
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break;
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case Instruction::SetNE:
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BuildMI (BB, X86::SETNE, 0, X86::AL);
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break;
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default:
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visitInstruction (I);
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break;
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}
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// Put it in the result using a move.
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switch (resultWidth)
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{
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case 1:
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BuildMI (BB, X86::MOVrr8, 1, resultReg).addReg (X86::AL);
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break;
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// FIXME: What to do about implicit destination registers?
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// E.g., you don't specify it, but CBW is more like AX = CBW(AL).
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case 2:
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BuildMI (BB, X86::CBW, 0, X86::AX);
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BuildMI (BB, X86::MOVrr16, 1, resultReg).addReg (X86::AX);
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break;
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case 4:
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BuildMI (BB, X86::CWDE, 0, X86::EAX);
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BuildMI (BB, X86::MOVrr32, 1, resultReg).addReg (X86::EAX);
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break;
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case 8:
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default:
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visitInstruction (I);
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break;
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}
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}
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/// 'ret' instruction - Here we are interested in meeting the x86 ABI. As such,
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@ -66,7 +66,6 @@ I(IDIVrr8 , "idivb", 0, 0) // AX/r8= AL&AH F6/6
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I(IDIVrr16 , "idivw", 0, 0) // DA/r16=AX&DX F7/6
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I(IDIVrr32 , "idivl", 0, 0) // DA/r32=EAX&DX F7/6
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// Logical operators
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I(ANDrr8 , "andb", 0, 0) // R8 &= R8 20/r
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I(ANDrr16 , "andw", 0, 0) // R16 &= R16 21/r
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@ -98,11 +97,39 @@ I(SARir16 , "sarw", 0, 0) // R16 >>= imm8 C1/7 ib
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I(SARrr32 , "sarl", 0, 0) // R32 >>= cl D3/7
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I(SARir32 , "sarl", 0, 0) // R32 >>= imm8 C1/7 ib
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// Floating point loads
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I(FLDr4 , "flds", 0, 0) // push float D9/0
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I(FLDr8 , "fldl ", 0, 0) // push double DD/0
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// Miscellaneous instructions...
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// Floating point compares
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I(FUCOMPP , "fucompp", 0, 0) // compare+pop2x DA E9
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// Floating point flag ops
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I(FNSTSWr8 , "fnstsw", 0, 0) // AX = fp flags DF E0
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// Condition code ops, incl. set if equal/not equal/...
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I(SAHF , "sahf", 0, 0) // flags = AH 9E
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I(SETA , "seta", 0, 0) // R8 = > unsign 0F 97
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I(SETAE , "setae", 0, 0) // R8 = >=unsign 0F 93
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I(SETB , "setb", 0, 0) // R8 = < unsign 0F 92
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I(SETBE , "setbe", 0, 0) // R8 = <=unsign 0F 96
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I(SETE , "sete", 0, 0) // R8 = == 0F 94
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I(SETG , "setg", 0, 0) // R8 = > signed 0F 9F
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I(SETGE , "setge", 0, 0) // R8 = >=signed 0F 9D
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I(SETL , "setl", 0, 0) // R8 = < signed 0F 9C
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I(SETLE , "setle", 0, 0) // R8 = <=signed 0F 9E
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I(SETNE , "setne", 0, 0) // R8 = != 0F 95
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// Integer comparisons
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I(CMPrr8 , "cmpb", 0, 0) // compare R8,R8 38/r
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I(CMPrr16 , "cmpw", 0, 0) // compare R16,R16 39/r
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I(CMPrr32 , "cmpl", 0, 0) // compare R32,R32 39/r
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// Sign extenders
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I(CBW , "cbw", 0, 0) // AH = signext(AL) 98
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I(CWD , "cwd", 0, 0) // DX = signext(AX) 99
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I(CWQ , "cwq", 0, 0) // EDX= signext(EAX) 99
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I(CWDE , "cwde", 0, 0) // EAX = extend AX 98
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// At this point, I is dead, so undefine the macro
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#undef I
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20
test/ExecutionEngine/test-setcond-fp.ll
Normal file
20
test/ExecutionEngine/test-setcond-fp.ll
Normal file
@ -0,0 +1,20 @@
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void %main() {
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%double1 = add double 0.0, 0.0
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%double2 = add double 0.0, 0.0
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%float1 = add float 0.0, 0.0
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%float2 = add float 0.0, 0.0
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%test49 = seteq float %float1, %float2
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%test50 = setge float %float1, %float2
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%test51 = setgt float %float1, %float2
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%test52 = setle float %float1, %float2
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%test53 = setlt float %float1, %float2
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%test54 = setne float %float1, %float2
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%test55 = seteq double %double1, %double2
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%test56 = setge double %double1, %double2
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%test57 = setgt double %double1, %double2
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%test58 = setle double %double1, %double2
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%test59 = setlt double %double1, %double2
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%test60 = setne double %double1, %double2
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ret void
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}
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68
test/ExecutionEngine/test-setcond-int.ll
Normal file
68
test/ExecutionEngine/test-setcond-int.ll
Normal file
@ -0,0 +1,68 @@
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void %main() {
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%int1 = add int 0, 0
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%int2 = add int 0, 0
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%long1 = add long 0, 0
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%long2 = add long 0, 0
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%sbyte1 = add sbyte 0, 0
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%sbyte2 = add sbyte 0, 0
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%short1 = add short 0, 0
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%short2 = add short 0, 0
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%ubyte1 = add ubyte 0, 0
|
||||
%ubyte2 = add ubyte 0, 0
|
||||
%uint1 = add uint 0, 0
|
||||
%uint2 = add uint 0, 0
|
||||
%ulong1 = add ulong 0, 0
|
||||
%ulong2 = add ulong 0, 0
|
||||
%ushort1 = add ushort 0, 0
|
||||
%ushort2 = add ushort 0, 0
|
||||
%test1 = seteq ubyte %ubyte1, %ubyte2
|
||||
%test2 = setge ubyte %ubyte1, %ubyte2
|
||||
%test3 = setgt ubyte %ubyte1, %ubyte2
|
||||
%test4 = setle ubyte %ubyte1, %ubyte2
|
||||
%test5 = setlt ubyte %ubyte1, %ubyte2
|
||||
%test6 = setne ubyte %ubyte1, %ubyte2
|
||||
%test7 = seteq ushort %ushort1, %ushort2
|
||||
%test8 = setge ushort %ushort1, %ushort2
|
||||
%test9 = setgt ushort %ushort1, %ushort2
|
||||
%test10 = setle ushort %ushort1, %ushort2
|
||||
%test11 = setlt ushort %ushort1, %ushort2
|
||||
%test12 = setne ushort %ushort1, %ushort2
|
||||
%test13 = seteq uint %uint1, %uint2
|
||||
%test14 = setge uint %uint1, %uint2
|
||||
%test15 = setgt uint %uint1, %uint2
|
||||
%test16 = setle uint %uint1, %uint2
|
||||
%test17 = setlt uint %uint1, %uint2
|
||||
%test18 = setne uint %uint1, %uint2
|
||||
%test19 = seteq ulong %ulong1, %ulong2
|
||||
%test20 = setge ulong %ulong1, %ulong2
|
||||
%test21 = setgt ulong %ulong1, %ulong2
|
||||
%test22 = setle ulong %ulong1, %ulong2
|
||||
%test23 = setlt ulong %ulong1, %ulong2
|
||||
%test24 = setne ulong %ulong1, %ulong2
|
||||
%test25 = seteq sbyte %sbyte1, %sbyte2
|
||||
%test26 = setge sbyte %sbyte1, %sbyte2
|
||||
%test27 = setgt sbyte %sbyte1, %sbyte2
|
||||
%test28 = setle sbyte %sbyte1, %sbyte2
|
||||
%test29 = setlt sbyte %sbyte1, %sbyte2
|
||||
%test30 = setne sbyte %sbyte1, %sbyte2
|
||||
%test31 = seteq short %short1, %short2
|
||||
%test32 = setge short %short1, %short2
|
||||
%test33 = setgt short %short1, %short2
|
||||
%test34 = setle short %short1, %short2
|
||||
%test35 = setlt short %short1, %short2
|
||||
%test36 = setne short %short1, %short2
|
||||
%test37 = seteq int %int1, %int2
|
||||
%test38 = setge int %int1, %int2
|
||||
%test39 = setgt int %int1, %int2
|
||||
%test40 = setle int %int1, %int2
|
||||
%test41 = setlt int %int1, %int2
|
||||
%test42 = setne int %int1, %int2
|
||||
%test43 = seteq long %long1, %long2
|
||||
%test44 = setge long %long1, %long2
|
||||
%test45 = setgt long %long1, %long2
|
||||
%test46 = setle long %long1, %long2
|
||||
%test47 = setlt long %long1, %long2
|
||||
%test48 = setne long %long1, %long2
|
||||
ret void
|
||||
}
|
||||
Loading…
x
Reference in New Issue
Block a user