6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-11-05 13:09:10 +00:00
Code Issues Projects Releases Wiki Activity

Add basic support for code generation of

Browse Source 
addrspace(257) -> FS relative on x86.  Patch by Zoltan Varga!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70992 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2009-05-05 18:52:19 +00:00
parent 26edc21b1b
commit 1777d0c6c5
4 changed files with 31 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

10
docs/CodeGenerator.html
View File

@ -1844,11 +1844,13 @@ OperandTy: VirtReg, | VirtReg, UnsImm, VirtReg, SignExtImm
segment. LLVM address space 0 is the default address space, which includes
the stack, and any unqualified memory accesses in a program. Address spaces
1-255 are currently reserved for user-defined code. The GS-segment is
represented by address space 256. Other x86 segments have yet to be
allocated address space numbers.</p>
represented by address space 256, while the FS-segment is represented by
address space 257. Other x86 segments have yet to be allocated address space
numbers.</p>
<p>Some operating systems use the GS-segment to implement TLS, so care should be
taken when reading and writing to address space 256 on these platforms.</p>
<p>Some operating systems use the FS/GS-segment to implement TLS, so care
should be taken when reading and writing to address space 256/257 on these
platforms.</p>
</div>

5
lib/Target/X86/X86Instr64bit.td
View File

@ -1326,6 +1326,11 @@ def MOV64GSrm : RI<0x8B, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
"movq\t%gs:$src, $dst",
[(set GR64:$dst, (gsload addr:$src))]>, SegGS;
let AddedComplexity = 5 in
def MOV64FSrm : RI<0x8B, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
"movq\t%fs:$src, $dst",
[(set GR64:$dst, (fsload addr:$src))]>, SegFS;
//===----------------------------------------------------------------------===//
// Atomic Instructions
//===----------------------------------------------------------------------===//

12
lib/Target/X86/X86InstrInfo.td
View File

@ -345,6 +345,13 @@ def gsload : PatFrag<(ops node:$ptr), (load node:$ptr), [{
return false;
}]>;
def fsload : PatFrag<(ops node:$ptr), (load node:$ptr), [{
if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue())
if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
return PT->getAddressSpace() == 257;
return false;
}]>;
def loadi8 : PatFrag<(ops node:$ptr), (i8 (load node:$ptr)), [{
if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue())
if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
@ -3004,6 +3011,11 @@ def GS_MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
"movl\t%gs:$src, $dst",
[(set GR32:$dst, (gsload addr:$src))]>, SegGS;
let AddedComplexity = 5 in
def FS_MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
"movl\t%fs:$src, $dst",
[(set GR32:$dst, (fsload addr:$src))]>, SegFS;
//===----------------------------------------------------------------------===//
// DWARF Pseudo Instructions
//

8
test/CodeGen/X86/movfs.ll Normal file
View File

@ -0,0 +1,8 @@
; RUN: llvm-as < %s | llc -march=x86 | grep fs
define i32 @foo() nounwind readonly {
entry:
%tmp = load i32* addrspace(257)* getelementptr (i32* addrspace(257)* inttoptr (i32 72 to i32* addrspace(257)*), i32 31) ; <i32*> [#uses=1]
%tmp1 = load i32* %tmp ; <i32> [#uses=1]
ret i32 %tmp1
}