6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-09-24 23:28:41 +00:00
Code Issues Projects Releases Wiki Activity

X86: Don't emit conditional floating point moves on when targeting pre-pentiumpro architectures.

Browse Source 
* Model FPSW (the FPU status word) as a register.
* Add ISel patterns for the FUCOM*, FNSTSW and SAHF instructions.
* During Legalize/Lowering, build a node sequence to transfer the comparison
result from FPSW into EFLAGS. If you're wondering about the right-shift: That's
an implicit sub-register extraction (%ax -> %ah) which is handled later on by
the instruction selector.

Fixes PR6679. Patch by Christoph Erhardt!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155704 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Benjamin Kramer
2012-04-27 12:07:43 +00:00
parent c84f975e6f
commit 17c836c4b5
7 changed files with 101 additions and 17 deletions
Download Patch File Download Diff File Expand all files Collapse all files

7
test/CodeGen/X86/fp-stack-compare.ll
View File

@@ -1,8 +1,11 @@
; RUN: llc < %s -march=x86 -mcpu=i386 | FileCheck %s
; PR1012
; PR6679
define float @foo(float* %col.2.0) {
; CHECK: fucompi
; CHECK: fucomp
; CHECK-NOT: fucompi
; CHECK: j
; CHECK-NOT: fcmov
%tmp = load float* %col.2.0
%tmp16 = fcmp olt float %tmp, 0.000000e+00
%tmp20 = fsub float -0.000000e+00, %tmp