6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-01-30 04:35:00 +00:00
Code Issues Projects Releases Wiki Activity

ARM some VFP tblgen'erated two-operand aliases.

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155178 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jim Grosbach 2012-04-20 00:15:00 +00:00
parent bfb3c5a50c
commit 181b147975
2 changed files with 15 additions and 18 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

24
lib/Target/ARM/ARMInstrVFP.td
View File

@ -221,11 +221,13 @@ defm : VFPDTAnyInstAlias<"vpop${p}", "$r",
// FP Binary Operations. // FP Binary Operations.
// //
let TwoOperandAliasConstraint = "$Dn = $Dd" in
def VADDD : ADbI<0b11100, 0b11, 0, 0, def VADDD : ADbI<0b11100, 0b11, 0, 0,
(outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm), (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm),
IIC_fpALU64, "vadd", ".f64\t$Dd, $Dn, $Dm", IIC_fpALU64, "vadd", ".f64\t$Dd, $Dn, $Dm",
[(set DPR:$Dd, (fadd DPR:$Dn, (f64 DPR:$Dm)))]>; [(set DPR:$Dd, (fadd DPR:$Dn, (f64 DPR:$Dm)))]>;
let TwoOperandAliasConstraint = "$Sn = $Sd" in
def VADDS : ASbIn<0b11100, 0b11, 0, 0, def VADDS : ASbIn<0b11100, 0b11, 0, 0,
(outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm), (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
IIC_fpALU32, "vadd", ".f32\t$Sd, $Sn, $Sm", IIC_fpALU32, "vadd", ".f32\t$Sd, $Sn, $Sm",
@ -235,11 +237,13 @@ def VADDS : ASbIn<0b11100, 0b11, 0, 0,
let D = VFPNeonA8Domain; let D = VFPNeonA8Domain;
} }
let TwoOperandAliasConstraint = "$Dn = $Dd" in
def VSUBD : ADbI<0b11100, 0b11, 1, 0, def VSUBD : ADbI<0b11100, 0b11, 1, 0,
(outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm), (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm),
IIC_fpALU64, "vsub", ".f64\t$Dd, $Dn, $Dm", IIC_fpALU64, "vsub", ".f64\t$Dd, $Dn, $Dm",
[(set DPR:$Dd, (fsub DPR:$Dn, (f64 DPR:$Dm)))]>; [(set DPR:$Dd, (fsub DPR:$Dn, (f64 DPR:$Dm)))]>;
let TwoOperandAliasConstraint = "$Sn = $Sd" in
def VSUBS : ASbIn<0b11100, 0b11, 1, 0, def VSUBS : ASbIn<0b11100, 0b11, 1, 0,
(outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm), (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
IIC_fpALU32, "vsub", ".f32\t$Sd, $Sn, $Sm", IIC_fpALU32, "vsub", ".f32\t$Sd, $Sn, $Sm",
@ -249,21 +253,25 @@ def VSUBS : ASbIn<0b11100, 0b11, 1, 0,
let D = VFPNeonA8Domain; let D = VFPNeonA8Domain;
} }
let TwoOperandAliasConstraint = "$Dn = $Dd" in
def VDIVD : ADbI<0b11101, 0b00, 0, 0, def VDIVD : ADbI<0b11101, 0b00, 0, 0,
(outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm), (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm),
IIC_fpDIV64, "vdiv", ".f64\t$Dd, $Dn, $Dm", IIC_fpDIV64, "vdiv", ".f64\t$Dd, $Dn, $Dm",
[(set DPR:$Dd, (fdiv DPR:$Dn, (f64 DPR:$Dm)))]>; [(set DPR:$Dd, (fdiv DPR:$Dn, (f64 DPR:$Dm)))]>;
let TwoOperandAliasConstraint = "$Sn = $Sd" in
def VDIVS : ASbI<0b11101, 0b00, 0, 0, def VDIVS : ASbI<0b11101, 0b00, 0, 0,
(outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm), (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
IIC_fpDIV32, "vdiv", ".f32\t$Sd, $Sn, $Sm", IIC_fpDIV32, "vdiv", ".f32\t$Sd, $Sn, $Sm",
[(set SPR:$Sd, (fdiv SPR:$Sn, SPR:$Sm))]>; [(set SPR:$Sd, (fdiv SPR:$Sn, SPR:$Sm))]>;
let TwoOperandAliasConstraint = "$Dn = $Dd" in
def VMULD : ADbI<0b11100, 0b10, 0, 0, def VMULD : ADbI<0b11100, 0b10, 0, 0,
(outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm), (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm),
IIC_fpMUL64, "vmul", ".f64\t$Dd, $Dn, $Dm", IIC_fpMUL64, "vmul", ".f64\t$Dd, $Dn, $Dm",
[(set DPR:$Dd, (fmul DPR:$Dn, (f64 DPR:$Dm)))]>; [(set DPR:$Dd, (fmul DPR:$Dn, (f64 DPR:$Dm)))]>;
let TwoOperandAliasConstraint = "$Sn = $Sd" in
def VMULS : ASbIn<0b11100, 0b10, 0, 0, def VMULS : ASbIn<0b11100, 0b10, 0, 0,
(outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm), (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
IIC_fpMUL32, "vmul", ".f32\t$Sd, $Sn, $Sm", IIC_fpMUL32, "vmul", ".f32\t$Sd, $Sn, $Sm",
@ -1426,22 +1434,6 @@ def : VFP2InstAlias<"vldr${p}.64 $Dd, $addr",
def : VFP2InstAlias<"vstr${p}.64 $Dd, $addr", def : VFP2InstAlias<"vstr${p}.64 $Dd, $addr",
(VSTRD DPR:$Dd, addrmode5:$addr, pred:$p)>; (VSTRD DPR:$Dd, addrmode5:$addr, pred:$p)>;
// VMUL has a two-operand form (implied destination operand)
def : VFP2InstAlias<"vmul${p}.f64 $Dn, $Dm",
(VMULD DPR:$Dn, DPR:$Dn, DPR:$Dm, pred:$p)>;
def : VFP2InstAlias<"vmul${p}.f32 $Sn, $Sm",
(VMULS SPR:$Sn, SPR:$Sn, SPR:$Sm, pred:$p)>;
// VADD has a two-operand form (implied destination operand)
def : VFP2InstAlias<"vadd${p}.f64 $Dn, $Dm",
(VADDD DPR:$Dn, DPR:$Dn, DPR:$Dm, pred:$p)>;
def : VFP2InstAlias<"vadd${p}.f32 $Sn, $Sm",
(VADDS SPR:$Sn, SPR:$Sn, SPR:$Sm, pred:$p)>;
// VSUB has a two-operand form (implied destination operand)
def : VFP2InstAlias<"vsub${p}.f64 $Dn, $Dm",
(VSUBD DPR:$Dn, DPR:$Dn, DPR:$Dm, pred:$p)>;
def : VFP2InstAlias<"vsub${p}.f32 $Sn, $Sm",
(VSUBS SPR:$Sn, SPR:$Sn, SPR:$Sm, pred:$p)>;
// VMOV can accept optional 32-bit or less data type suffix suffix. // VMOV can accept optional 32-bit or less data type suffix suffix.
def : VFP2InstAlias<"vmov${p}.8 $Rt, $Sn", def : VFP2InstAlias<"vmov${p}.8 $Rt, $Sn",
(VMOVRS GPR:$Rt, SPR:$Sn, pred:$p)>; (VMOVRS GPR:$Rt, SPR:$Sn, pred:$p)>;

5
test/MC/ARM/simple-fp-encoding.s
View File

@ -12,9 +12,14 @@
vdiv.f64 d16, d17, d16 vdiv.f64 d16, d17, d16
vdiv.f32 s0, s1, s0 vdiv.f32 s0, s1, s0
vdiv.f32 s5, s7
vdiv.f64 d5, d7
@ CHECK: vdiv.f64 d16, d17, d16 @ encoding: [0xa0,0x0b,0xc1,0xee] @ CHECK: vdiv.f64 d16, d17, d16 @ encoding: [0xa0,0x0b,0xc1,0xee]
@ CHECK: vdiv.f32 s0, s1, s0 @ encoding: [0x80,0x0a,0x80,0xee] @ CHECK: vdiv.f32 s0, s1, s0 @ encoding: [0x80,0x0a,0x80,0xee]
@ CHECK: vdiv.f32 s5, s5, s7 @ encoding: [0xa3,0x2a,0xc2,0xee]
@ CHECK: vdiv.f64 d5, d5, d7 @ encoding: [0x07,0x5b,0x85,0xee]
vmul.f64 d16, d17, d16 vmul.f64 d16, d17, d16
vmul.f64 d20, d17 vmul.f64 d20, d17